2 * Copyright 2010-2012 Freescale Semiconductor, Inc.
4 * Authors: Roy Zang <tie-fei.zang@freescale.com>
5 * Chunhe Lan <b25806@freescale.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/cache.h>
31 #include <asm/processor.h>
33 #include <asm/immap_85xx.h>
34 #include <asm/fsl_pci.h>
35 #include <asm/fsl_ddr_sdram.h>
36 #include <asm/fsl_portals.h>
38 #include <fdt_support.h>
45 #include <asm/fsl_dtsec.h>
49 DECLARE_GLOBAL_DATA_PTR;
51 int board_early_init_f(void)
53 fsl_lbc_t *lbc = LBC_BASE_ADDR;
55 /* Set ABSWP to implement conversion of addresses in the LBC */
56 setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
63 u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR;
65 printf("Board: P1023 RDS\n");
67 clrbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG_CLR);
68 setbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG0);
73 /* Fixed sdram init -- doesn't use serial presence detect. */
74 phys_size_t fixed_sdram(void)
76 #ifndef CONFIG_SYS_RAMBOOT
77 ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
79 set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
81 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
82 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
83 out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
84 out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
85 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
86 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
87 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
88 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
89 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
90 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
91 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
92 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
93 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
94 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
95 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
96 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
97 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
98 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
99 out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
100 out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
101 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
103 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024ul;
107 void pci_init_board(void)
109 fsl_pcie_init_board(0);
113 int board_early_init_r(void)
115 const unsigned int flashbase = CONFIG_SYS_BCSR_BASE;
116 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
119 * Remap Boot flash + BCSR region to caching-inhibited
120 * so that flash can be erased properly.
123 /* Flush d-cache and invalidate i-cache of any FLASH data */
127 /* invalidate existing TLB entry for flash + bcsr */
128 disable_tlb(flash_esel);
130 set_tlb(1, flashbase, CONFIG_SYS_BCSR_BASE_PHYS,
131 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
132 0, flash_esel, BOOKE_PAGESZ_256M, 1);
139 unsigned long get_board_sys_clk(ulong dummy)
144 unsigned long get_board_ddr_clk(ulong dummy)
149 int board_eth_init(bd_t *bis)
151 u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR;
152 ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
153 struct fsl_pq_mdio_info dtsec_mdio_info;
156 * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
159 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
161 dtsec_mdio_info.regs =
162 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
163 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
165 /* Register the 1G MDIO bus */
166 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
168 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
169 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
171 fm_info_set_mdio(FM1_DTSEC1,
172 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
173 fm_info_set_mdio(FM1_DTSEC2,
174 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
176 /* Make SERDES connected to SGMII by cleaing bcsr19[7] */
177 if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII)
178 clrbits_8(&bcsr[19], BCSR19_SGMII_SEL_L);
180 #ifdef CONFIG_FMAN_ENET
184 return pci_eth_init(bis);
187 #if defined(CONFIG_OF_BOARD_SETUP)
188 void ft_board_setup(void *blob, bd_t *bd)
193 ft_cpu_setup(blob, bd);
195 base = getenv_bootm_low();
196 size = getenv_bootm_size();
198 fdt_fixup_memory(blob, (u64)base, (u64)size);
200 /* By default NOR is on, and NAND is disabled */
201 #ifdef CONFIG_NAND_U_BOOT
202 do_fixup_by_path_string(blob, "nor_flash", "status", "disabled");
203 do_fixup_by_path_string(blob, "nand_flash", "status", "okay");
205 #ifdef CONFIG_HAS_FSL_DR_USB
206 fdt_fixup_dr_usb(blob, bd);
209 fdt_fixup_fman_ethernet(blob);