2 * Copyright 2007-2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
35 #include <fdt_support.h>
37 #include <asm/fsl_law.h>
40 #include "../common/pixis.h"
41 #include "../common/sgmii_riser.h"
43 DECLARE_GLOBAL_DATA_PTR;
45 phys_size_t fixed_sdram(void);
49 puts("Board: P2020DS ");
50 #ifdef CONFIG_PHYS_64BIT
51 puts("(36-bit addrmap) ");
53 printf("Sys ID: 0x%02x, "
54 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
55 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
56 in8(PIXIS_BASE + PIXIS_PVER));
60 phys_size_t initdram(int board_type)
62 phys_size_t dram_size = 0;
64 puts("Initializing....");
66 #ifdef CONFIG_SPD_EEPROM
67 dram_size = fsl_ddr_sdram();
69 dram_size = fixed_sdram();
71 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
73 LAW_TRGT_IF_DDR) < 0) {
74 printf("ERROR setting Local Access Windows for DDR\n");
78 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
79 dram_size *= 0x100000;
85 #if !defined(CONFIG_SPD_EEPROM)
87 * Fixed sdram init -- doesn't use serial presence detect.
90 phys_size_t fixed_sdram(void)
92 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
95 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
96 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
97 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
98 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
99 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
100 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
101 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
102 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
103 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
104 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
105 ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
106 ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
107 ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
108 ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
109 ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
111 if (!strcmp("performance", getenv("perf_mode"))) {
112 /* Performance Mode Values */
114 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
115 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
116 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
117 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
118 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
124 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
126 /* Stable Mode Values */
128 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
129 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
130 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
131 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
132 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
134 /* ECC will be assumed in stable mode */
135 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
136 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
137 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
143 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
146 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
148 debug("DDR - 1st controller: memory initializing\n");
150 * Poll until memory is initialized.
151 * 512 Meg at 400 might hit this 200 times or so.
153 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
155 debug("DDR: memory initialized\n\n");
160 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
166 static struct pci_controller pcie1_hose;
170 static struct pci_controller pcie2_hose;
174 static struct pci_controller pcie3_hose;
177 int first_free_busno = 0;
180 void pci_init_board(void)
182 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
183 uint devdisr = gur->devdisr;
184 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
185 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
187 volatile ccsr_fsl_pci_t *pci;
188 struct pci_controller *hose;
189 int pcie_ep, pcie_configured;
190 struct pci_region *r;
193 debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
194 devdisr, io_sel, host_agent);
196 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
197 printf(" eTSEC2 is in sgmii mode.\n");
198 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
199 printf(" eTSEC3 is in sgmii mode.\n");
202 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
204 pcie_ep = (host_agent == 2) || (host_agent == 4) ||
205 (host_agent == 6) || (host_agent == 0);
206 pcie_configured = (io_sel == 0x2) || (io_sel == 0xe);
209 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
210 printf("\n PCIE2 connected to ULI as %s (base addr %x)",
211 pcie_ep ? "End Point" : "Root Complex",
213 if (pci->pme_msg_det) {
214 pci->pme_msg_det = 0xffffffff;
215 debug(" with errors. Clearing. Now 0x%08x",
221 r += fsl_pci_setup_inbound_windows(r);
223 /* outbound memory */
225 CONFIG_SYS_PCIE2_MEM_BUS,
226 CONFIG_SYS_PCIE2_MEM_PHYS,
227 CONFIG_SYS_PCIE2_MEM_SIZE,
232 CONFIG_SYS_PCIE2_IO_BUS,
233 CONFIG_SYS_PCIE2_IO_PHYS,
234 CONFIG_SYS_PCIE2_IO_SIZE,
237 hose->region_count = r - hose->regions;
238 hose->first_busno = first_free_busno;
239 pci_setup_indirect(hose, (int)&pci->cfg_addr,
240 (int)&pci->cfg_data);
243 first_free_busno = hose->last_busno+1;
244 printf(" PCIE2 on bus %02x - %02x\n",
245 hose->first_busno, hose->last_busno);
248 * The workaround doesn't work on p2020 because the location
249 * we try and read isn't valid on p2020, fix this later
253 * Activate ULI1575 legacy chip by performing a fake
254 * memory access. Needed to make ULI RTC work.
255 * Device 1d has the first on-board memory BAR.
258 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
259 PCI_BASE_ADDRESS_1, &temp32);
260 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
261 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
263 debug(" uli1575 read to %p\n", p);
268 printf(" PCIE2: disabled\n");
271 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
275 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
277 pcie_ep = (host_agent == 0) || (host_agent == 3) ||
278 (host_agent == 5) || (host_agent == 6);
279 pcie_configured = (io_sel == 0x2) || (io_sel == 0x4);
282 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
283 printf("\n PCIE3 connected to Slot 1 as %s (base addr %x)",
284 pcie_ep ? "End Point" : "Root Complex",
286 if (pci->pme_msg_det) {
287 pci->pme_msg_det = 0xffffffff;
288 debug(" with errors. Clearing. Now 0x%08x",
294 r += fsl_pci_setup_inbound_windows(r);
296 /* outbound memory */
298 CONFIG_SYS_PCIE3_MEM_BUS,
299 CONFIG_SYS_PCIE3_MEM_PHYS,
300 CONFIG_SYS_PCIE3_MEM_SIZE,
305 CONFIG_SYS_PCIE3_IO_BUS,
306 CONFIG_SYS_PCIE3_IO_PHYS,
307 CONFIG_SYS_PCIE3_IO_SIZE,
310 hose->region_count = r - hose->regions;
311 hose->first_busno = first_free_busno;
312 pci_setup_indirect(hose, (int)&pci->cfg_addr,
313 (int)&pci->cfg_data);
317 first_free_busno = hose->last_busno+1;
318 printf(" PCIE3 on bus %02x - %02x\n",
319 hose->first_busno, hose->last_busno);
322 printf(" PCIE3: disabled\n");
325 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
329 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
331 pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5);
332 pcie_configured = (io_sel & 6) || (io_sel == 0xE) || (io_sel == 0xF);
335 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
336 printf("\n PCIE1 connected to Slot 2 as %s (base addr %x)",
337 pcie_ep ? "End Point" : "Root Complex",
339 if (pci->pme_msg_det) {
340 pci->pme_msg_det = 0xffffffff;
341 debug(" with errors. Clearing. Now 0x%08x",
347 r += fsl_pci_setup_inbound_windows(r);
349 /* outbound memory */
351 CONFIG_SYS_PCIE1_MEM_BUS,
352 CONFIG_SYS_PCIE1_MEM_PHYS,
353 CONFIG_SYS_PCIE1_MEM_SIZE,
358 CONFIG_SYS_PCIE1_IO_BUS,
359 CONFIG_SYS_PCIE1_IO_PHYS,
360 CONFIG_SYS_PCIE1_IO_SIZE,
363 hose->region_count = r - hose->regions;
364 hose->first_busno = first_free_busno;
366 pci_setup_indirect(hose, (int)&pci->cfg_addr,
367 (int)&pci->cfg_data);
371 first_free_busno = hose->last_busno+1;
372 printf(" PCIE1 on bus %02x - %02x\n",
373 hose->first_busno, hose->last_busno);
376 printf(" PCIE1: disabled\n");
379 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
384 int board_early_init_r(void)
386 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
387 const u8 flash_esel = 2;
390 * Remap Boot flash + PROMJET region to caching-inhibited
391 * so that flash can be erased properly.
394 /* Flush d-cache and invalidate i-cache of any FLASH data */
398 /* invalidate existing TLB entry for flash + promjet */
399 disable_tlb(flash_esel);
401 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
402 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
403 0, flash_esel, BOOKE_PAGESZ_256M, 1);
408 #ifdef CONFIG_GET_CLK_FROM_ICS307
409 /* decode S[0-2] to Output Divider (OD) */
410 static unsigned char ics307_S_to_OD[] = {
411 10, 2, 8, 4, 5, 7, 3, 6
414 /* Calculate frequency being generated by ICS307-02 clock chip based upon
415 * the control bytes being programmed into it. */
416 /* XXX: This function should probably go into a common library */
418 ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
420 const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
421 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
422 unsigned long RDW = cw2 & 0x7F;
423 unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
426 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
428 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
429 * cw1: V8 V7 V6 V5 V4 V3 V2 V1
430 * cw2: V0 R6 R5 R4 R3 R2 R1 R0
432 * R6:R0 = Reference Divider Word (RDW)
433 * V8:V0 = VCO Divider Word (VDW)
434 * S2:S0 = Output Divider Select (OD)
435 * F1:F0 = Function of CLK2 Output
437 * C1:C0 = internal load capacitance for cyrstal
440 /* Adding 1 to get a "nicely" rounded number, but this needs
441 * more tweaking to get a "properly" rounded number. */
443 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
445 debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
450 unsigned long get_board_sys_clk(ulong dummy)
455 unsigned long get_board_ddr_clk(ulong dummy)
461 calculate_board_sys_clk(ulong dummy)
464 val = ics307_clk_freq(
465 in8(PIXIS_BASE + PIXIS_VSYSCLK0),
466 in8(PIXIS_BASE + PIXIS_VSYSCLK1),
467 in8(PIXIS_BASE + PIXIS_VSYSCLK2));
468 debug("sysclk val = %lu\n", val);
473 calculate_board_ddr_clk(ulong dummy)
476 val = ics307_clk_freq(
477 in8(PIXIS_BASE + PIXIS_VDDRCLK0),
478 in8(PIXIS_BASE + PIXIS_VDDRCLK1),
479 in8(PIXIS_BASE + PIXIS_VDDRCLK2));
480 debug("ddrclk val = %lu\n", val);
484 unsigned long get_board_sys_clk(ulong dummy)
489 i = in8(PIXIS_BASE + PIXIS_SPD);
522 unsigned long get_board_ddr_clk(ulong dummy)
527 i = in8(PIXIS_BASE + PIXIS_SPD);
561 #ifdef CONFIG_TSEC_ENET
562 int board_eth_init(bd_t *bis)
564 struct tsec_info_struct tsec_info[4];
565 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
569 SET_STD_TSEC_INFO(tsec_info[num], 1);
573 SET_STD_TSEC_INFO(tsec_info[num], 2);
574 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
575 tsec_info[num].flags |= TSEC_SGMII;
579 SET_STD_TSEC_INFO(tsec_info[num], 3);
580 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
581 tsec_info[num].flags |= TSEC_SGMII;
586 printf("No TSECs initialized\n");
591 #ifdef CONFIG_FSL_SGMII_RISER
592 fsl_sgmii_riser_init(tsec_info, num);
595 tsec_eth_init(bis, tsec_info, num);
601 #if defined(CONFIG_OF_BOARD_SETUP)
602 void ft_board_setup(void *blob, bd_t *bd)
607 ft_cpu_setup(blob, bd);
609 base = getenv_bootm_low();
610 size = getenv_bootm_size();
612 fdt_fixup_memory(blob, (u64)base, (u64)size);
615 ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
618 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
621 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
623 #ifdef CONFIG_FSL_SGMII_RISER
624 fsl_sgmii_riser_fdt_fixup(blob);
630 void board_lmb_reserve(struct lmb *lmb)
632 cpu_mp_lmb_reserve(lmb);