2 * Copyright 2007-2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
35 #include <fdt_support.h>
37 #include <asm/fsl_law.h>
41 #include "../common/pixis.h"
42 #include "../common/sgmii_riser.h"
44 DECLARE_GLOBAL_DATA_PTR;
46 phys_size_t fixed_sdram(void);
51 u8 *pixis_base = (u8 *)PIXIS_BASE;
53 puts("Board: P2020DS ");
54 #ifdef CONFIG_PHYS_64BIT
55 puts("(36-bit addrmap) ");
58 printf("Sys ID: 0x%02x, "
59 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
60 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
61 in_8(pixis_base + PIXIS_PVER));
63 sw7 = in_8(pixis_base + PIXIS_SW(7));
64 switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
67 printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
78 phys_size_t initdram(int board_type)
80 phys_size_t dram_size = 0;
82 puts("Initializing....");
84 #ifdef CONFIG_SPD_EEPROM
85 dram_size = fsl_ddr_sdram();
87 dram_size = fixed_sdram();
89 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
91 LAW_TRGT_IF_DDR) < 0) {
92 printf("ERROR setting Local Access Windows for DDR\n");
96 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
97 dram_size *= 0x100000;
103 #if !defined(CONFIG_SPD_EEPROM)
105 * Fixed sdram init -- doesn't use serial presence detect.
108 phys_size_t fixed_sdram(void)
110 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
113 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
114 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
115 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
116 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
117 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
118 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
119 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
120 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
121 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
122 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
123 ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
124 ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
125 ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
126 ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
127 ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
129 if (!strcmp("performance", getenv("perf_mode"))) {
130 /* Performance Mode Values */
132 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
133 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
134 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
135 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
136 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
142 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
144 /* Stable Mode Values */
146 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
147 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
148 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
149 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
150 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
152 /* ECC will be assumed in stable mode */
153 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
154 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
155 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
161 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
164 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
166 debug("DDR - 1st controller: memory initializing\n");
168 * Poll until memory is initialized.
169 * 512 Meg at 400 might hit this 200 times or so.
171 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
173 debug("DDR: memory initialized\n\n");
178 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
184 static struct pci_controller pcie1_hose;
188 static struct pci_controller pcie2_hose;
192 static struct pci_controller pcie3_hose;
195 int first_free_busno = 0;
198 void pci_init_board(void)
200 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
201 uint devdisr = gur->devdisr;
202 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
203 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
205 volatile ccsr_fsl_pci_t *pci;
206 struct pci_controller *hose;
207 int pcie_ep, pcie_configured;
208 struct pci_region *r;
211 debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
212 devdisr, io_sel, host_agent);
214 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
215 printf(" eTSEC2 is in sgmii mode.\n");
216 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
217 printf(" eTSEC3 is in sgmii mode.\n");
220 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
222 pcie_ep = (host_agent == 2) || (host_agent == 4) ||
223 (host_agent == 6) || (host_agent == 0);
224 pcie_configured = (io_sel == 0x2) || (io_sel == 0xe);
227 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
228 printf("\n PCIE2 connected to ULI as %s (base addr %x)",
229 pcie_ep ? "End Point" : "Root Complex",
231 if (pci->pme_msg_det) {
232 pci->pme_msg_det = 0xffffffff;
233 debug(" with errors. Clearing. Now 0x%08x",
239 r += fsl_pci_setup_inbound_windows(r);
241 /* outbound memory */
243 CONFIG_SYS_PCIE2_MEM_BUS,
244 CONFIG_SYS_PCIE2_MEM_PHYS,
245 CONFIG_SYS_PCIE2_MEM_SIZE,
250 CONFIG_SYS_PCIE2_IO_BUS,
251 CONFIG_SYS_PCIE2_IO_PHYS,
252 CONFIG_SYS_PCIE2_IO_SIZE,
255 hose->region_count = r - hose->regions;
256 hose->first_busno = first_free_busno;
257 pci_setup_indirect(hose, (int)&pci->cfg_addr,
258 (int)&pci->cfg_data);
261 first_free_busno = hose->last_busno+1;
262 printf(" PCIE2 on bus %02x - %02x\n",
263 hose->first_busno, hose->last_busno);
266 * The workaround doesn't work on p2020 because the location
267 * we try and read isn't valid on p2020, fix this later
271 * Activate ULI1575 legacy chip by performing a fake
272 * memory access. Needed to make ULI RTC work.
273 * Device 1d has the first on-board memory BAR.
276 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
277 PCI_BASE_ADDRESS_1, &temp32);
278 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
279 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
281 debug(" uli1575 read to %p\n", p);
286 printf(" PCIE2: disabled\n");
289 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
293 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
295 pcie_ep = (host_agent == 0) || (host_agent == 3) ||
296 (host_agent == 5) || (host_agent == 6);
297 pcie_configured = (io_sel == 0x2) || (io_sel == 0x4);
300 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
301 printf("\n PCIE3 connected to Slot 1 as %s (base addr %x)",
302 pcie_ep ? "End Point" : "Root Complex",
304 if (pci->pme_msg_det) {
305 pci->pme_msg_det = 0xffffffff;
306 debug(" with errors. Clearing. Now 0x%08x",
312 r += fsl_pci_setup_inbound_windows(r);
314 /* outbound memory */
316 CONFIG_SYS_PCIE3_MEM_BUS,
317 CONFIG_SYS_PCIE3_MEM_PHYS,
318 CONFIG_SYS_PCIE3_MEM_SIZE,
323 CONFIG_SYS_PCIE3_IO_BUS,
324 CONFIG_SYS_PCIE3_IO_PHYS,
325 CONFIG_SYS_PCIE3_IO_SIZE,
328 hose->region_count = r - hose->regions;
329 hose->first_busno = first_free_busno;
330 pci_setup_indirect(hose, (int)&pci->cfg_addr,
331 (int)&pci->cfg_data);
335 first_free_busno = hose->last_busno+1;
336 printf(" PCIE3 on bus %02x - %02x\n",
337 hose->first_busno, hose->last_busno);
340 printf(" PCIE3: disabled\n");
343 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
347 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
349 pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5);
350 pcie_configured = (io_sel & 6) || (io_sel == 0xE) || (io_sel == 0xF);
353 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
354 printf("\n PCIE1 connected to Slot 2 as %s (base addr %x)",
355 pcie_ep ? "End Point" : "Root Complex",
357 if (pci->pme_msg_det) {
358 pci->pme_msg_det = 0xffffffff;
359 debug(" with errors. Clearing. Now 0x%08x",
365 r += fsl_pci_setup_inbound_windows(r);
367 /* outbound memory */
369 CONFIG_SYS_PCIE1_MEM_BUS,
370 CONFIG_SYS_PCIE1_MEM_PHYS,
371 CONFIG_SYS_PCIE1_MEM_SIZE,
376 CONFIG_SYS_PCIE1_IO_BUS,
377 CONFIG_SYS_PCIE1_IO_PHYS,
378 CONFIG_SYS_PCIE1_IO_SIZE,
381 hose->region_count = r - hose->regions;
382 hose->first_busno = first_free_busno;
384 pci_setup_indirect(hose, (int)&pci->cfg_addr,
385 (int)&pci->cfg_data);
389 first_free_busno = hose->last_busno+1;
390 printf(" PCIE1 on bus %02x - %02x\n",
391 hose->first_busno, hose->last_busno);
394 printf(" PCIE1: disabled\n");
397 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
402 int board_early_init_r(void)
404 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
405 const u8 flash_esel = 2;
408 * Remap Boot flash + PROMJET region to caching-inhibited
409 * so that flash can be erased properly.
412 /* Flush d-cache and invalidate i-cache of any FLASH data */
416 /* invalidate existing TLB entry for flash + promjet */
417 disable_tlb(flash_esel);
419 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
420 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
421 0, flash_esel, BOOKE_PAGESZ_256M, 1);
426 #ifdef CONFIG_GET_CLK_FROM_ICS307
427 /* decode S[0-2] to Output Divider (OD) */
428 static unsigned char ics307_S_to_OD[] = {
429 10, 2, 8, 4, 5, 7, 3, 6
432 /* Calculate frequency being generated by ICS307-02 clock chip based upon
433 * the control bytes being programmed into it. */
434 /* XXX: This function should probably go into a common library */
436 ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
438 const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
439 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
440 unsigned long RDW = cw2 & 0x7F;
441 unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
444 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
446 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
447 * cw1: V8 V7 V6 V5 V4 V3 V2 V1
448 * cw2: V0 R6 R5 R4 R3 R2 R1 R0
450 * R6:R0 = Reference Divider Word (RDW)
451 * V8:V0 = VCO Divider Word (VDW)
452 * S2:S0 = Output Divider Select (OD)
453 * F1:F0 = Function of CLK2 Output
455 * C1:C0 = internal load capacitance for cyrstal
458 /* Adding 1 to get a "nicely" rounded number, but this needs
459 * more tweaking to get a "properly" rounded number. */
461 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
463 debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
468 unsigned long get_board_sys_clk(ulong dummy)
473 unsigned long get_board_ddr_clk(ulong dummy)
479 calculate_board_sys_clk(ulong dummy)
482 val = ics307_clk_freq(
483 in8(PIXIS_BASE + PIXIS_VSYSCLK0),
484 in8(PIXIS_BASE + PIXIS_VSYSCLK1),
485 in8(PIXIS_BASE + PIXIS_VSYSCLK2));
486 debug("sysclk val = %lu\n", val);
491 calculate_board_ddr_clk(ulong dummy)
494 val = ics307_clk_freq(
495 in8(PIXIS_BASE + PIXIS_VDDRCLK0),
496 in8(PIXIS_BASE + PIXIS_VDDRCLK1),
497 in8(PIXIS_BASE + PIXIS_VDDRCLK2));
498 debug("ddrclk val = %lu\n", val);
502 unsigned long get_board_sys_clk(ulong dummy)
507 i = in8(PIXIS_BASE + PIXIS_SPD);
540 unsigned long get_board_ddr_clk(ulong dummy)
545 i = in8(PIXIS_BASE + PIXIS_SPD);
579 #ifdef CONFIG_TSEC_ENET
580 int board_eth_init(bd_t *bis)
582 struct tsec_info_struct tsec_info[4];
583 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
587 SET_STD_TSEC_INFO(tsec_info[num], 1);
591 SET_STD_TSEC_INFO(tsec_info[num], 2);
592 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
593 tsec_info[num].flags |= TSEC_SGMII;
597 SET_STD_TSEC_INFO(tsec_info[num], 3);
598 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
599 tsec_info[num].flags |= TSEC_SGMII;
604 printf("No TSECs initialized\n");
609 #ifdef CONFIG_FSL_SGMII_RISER
610 fsl_sgmii_riser_init(tsec_info, num);
613 tsec_eth_init(bis, tsec_info, num);
615 return pci_eth_init(bis);
619 #if defined(CONFIG_OF_BOARD_SETUP)
620 void ft_board_setup(void *blob, bd_t *bd)
625 ft_cpu_setup(blob, bd);
627 base = getenv_bootm_low();
628 size = getenv_bootm_size();
630 fdt_fixup_memory(blob, (u64)base, (u64)size);
633 ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
636 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
639 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
641 #ifdef CONFIG_FSL_SGMII_RISER
642 fsl_sgmii_riser_fdt_fixup(blob);
648 void board_lmb_reserve(struct lmb *lmb)
650 cpu_mp_lmb_reserve(lmb);