2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h>
23 #include "../common/sleep.h"
24 #include "../common/qixis.h"
26 #include "t1040qds_qixis.h"
28 DECLARE_GLOBAL_DATA_PTR;
34 struct cpu_type *cpu = gd->arch.cpu;
35 static const char *const freq[] = {"100", "125", "156.25", "161.13",
36 "122.88", "122.88", "122.88"};
39 printf("Board: %sQDS, ", cpu->name);
40 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
41 QIXIS_READ(id), QIXIS_READ(arch));
43 sw = QIXIS_READ(brdcfg[0]);
44 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
47 printf("vBank: %d\n", sw);
55 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
57 printf("FPGA: v%d (%s), build %d",
58 (int)QIXIS_READ(scver), qixis_read_tag(buf),
59 (int)qixis_read_minor());
60 /* the timestamp string contains "\n" at the end */
61 printf(" on %s", qixis_read_time(buf));
64 * Display the actual SERDES reference clocks as configured by the
65 * dip switches on the board. Note that the SWx registers could
66 * technically be set to force the reference clocks to match the
67 * values that the SERDES expects (or vice versa). For now, however,
68 * we just display both values and hope the user notices when they
71 puts("SERDES Reference: ");
72 sw = QIXIS_READ(brdcfg[2]);
73 clock = (sw >> 6) & 3;
74 printf("Clock1=%sMHz ", freq[clock]);
75 clock = (sw >> 4) & 3;
76 printf("Clock2=%sMHz\n", freq[clock]);
81 int select_i2c_ch_pca9547(u8 ch)
85 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
87 puts("PCA: failed to select proper channel\n");
94 static void qe_board_setup(void)
98 if (hwconfig("qe") && hwconfig("tdm")) {
99 brdcfg15 = QIXIS_READ(brdcfg[15]);
101 * TDMRiser uses QE-TDM
102 * Route QE_TDM signals to TDM Riser slot
104 QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
105 } else if (hwconfig("qe") && hwconfig("uart")) {
106 brdcfg15 = QIXIS_READ(brdcfg[15]);
107 brdcfg9 = QIXIS_READ(brdcfg[9]);
109 * Route QE_TDM signals to UCC
110 * ProfiBus controlled by UCC3
113 QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
114 QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
118 int board_early_init_f(void)
120 #if defined(CONFIG_DEEP_SLEEP)
122 fsl_dp_disable_console();
128 int board_early_init_r(void)
130 #ifdef CONFIG_SYS_FLASH_BASE
131 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
132 int flash_esel = find_tlb_idx((void *)flashbase, 1);
135 * Remap Boot flash + PROMJET region to caching-inhibited
136 * so that flash can be erased properly.
139 /* Flush d-cache and invalidate i-cache of any FLASH data */
143 if (flash_esel == -1) {
144 /* very unlikely unless something is messed up */
145 puts("Error: Could not find TLB for FLASH BASE\n");
146 flash_esel = 2; /* give our best effort to continue */
148 /* invalidate existing TLB entry for flash + promjet */
149 disable_tlb(flash_esel);
152 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
153 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
154 0, flash_esel, BOOKE_PAGESZ_256M, 1);
157 #ifdef CONFIG_SYS_DPAA_QBMAN
160 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
165 unsigned long get_board_sys_clk(void)
167 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
169 switch (sysclk_conf & 0x0F) {
170 case QIXIS_SYSCLK_64:
172 case QIXIS_SYSCLK_83:
174 case QIXIS_SYSCLK_100:
176 case QIXIS_SYSCLK_125:
178 case QIXIS_SYSCLK_133:
180 case QIXIS_SYSCLK_150:
182 case QIXIS_SYSCLK_160:
184 case QIXIS_SYSCLK_166:
190 unsigned long get_board_ddr_clk(void)
192 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
194 switch ((ddrclk_conf & 0x30) >> 4) {
195 case QIXIS_DDRCLK_100:
197 case QIXIS_DDRCLK_125:
199 case QIXIS_DDRCLK_133:
205 #define NUM_SRDS_BANKS 2
206 int misc_init_r(void)
209 serdes_corenet_t *srds_regs =
210 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
211 u32 actual[NUM_SRDS_BANKS] = { 0 };
214 sw = QIXIS_READ(brdcfg[2]);
215 for (i = 0; i < NUM_SRDS_BANKS; i++) {
216 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
219 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
222 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
225 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
231 for (i = 0; i < NUM_SRDS_BANKS; i++) {
232 u32 pllcr0 = srds_regs->bank[i].pllcr0;
233 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
234 if (expected != actual[i]) {
235 printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
236 i + 1, serdes_clock_to_string(expected),
237 serdes_clock_to_string(actual[i]));
246 int ft_board_setup(void *blob, bd_t *bd)
251 ft_cpu_setup(blob, bd);
253 base = getenv_bootm_low();
254 size = getenv_bootm_size();
256 fdt_fixup_memory(blob, (u64)base, (u64)size);
259 pci_of_setup(blob, bd);
262 fdt_fixup_liodn(blob);
264 #ifdef CONFIG_HAS_FSL_DR_USB
265 fdt_fixup_dr_usb(blob, bd);
268 #ifdef CONFIG_SYS_DPAA_FMAN
269 fdt_fixup_fman_ethernet(blob);
270 fdt_fixup_board_enet(blob);
276 void qixis_dump_switch(void)
280 QIXIS_WRITE(cms[0], 0x00);
281 nr_of_cfgsw = QIXIS_READ(cms[1]);
283 puts("DIP switch settings dump:\n");
284 for (i = 1; i <= nr_of_cfgsw; i++) {
285 QIXIS_WRITE(cms[0], i);
286 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
290 int board_need_mem_reset(void)