2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 dimm_params_t ddr_raw_timing = {
11 .rank_density = 2147483648u,
12 .capacity = 4294967296u,
13 .primary_sdram_width = 64,
19 .n_banks_per_sdram_device = 8,
20 .edc_config = 2, /* ECC */
21 .burst_lengths_bitmask = 0x0c,
23 .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */
34 .refresh_rate_ps = 7800000,
38 struct board_specific_parameters {
40 u32 datarate_mhz_high;
49 * These tables contain all valid speeds we want to override with board
50 * specific parameters. datarate_mhz_high values need to be in ascending order
51 * for each n_ranks group.
54 static const struct board_specific_parameters udimm0[] = {
57 * num| hi| rank| clk| wrlvl | wrlvl
58 * ranks| mhz| GB |adjst| start | ctl2
60 {2, 833, 4, 4, 6, 0x06060607, 0x08080807},
61 {2, 833, 0, 4, 6, 0x06060607, 0x08080807},
62 {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
63 {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
64 {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
65 {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
66 {1, 833, 4, 4, 6, 0x06060607, 0x08080807},
67 {1, 833, 0, 4, 6, 0x06060607, 0x08080807},
68 {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
69 {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
70 {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
71 {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
75 static const struct board_specific_parameters *udimms[] = {