2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/compiler.h>
12 #include <asm/processor.h>
13 #include <asm/cache.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
20 #include "../common/sleep.h"
24 DECLARE_GLOBAL_DATA_PTR;
28 struct cpu_type *cpu = gd->arch.cpu;
31 #ifdef CONFIG_T104XD4RDB
32 printf("Board: %sD4RDB\n", cpu->name);
34 printf("Board: %sRDB\n", cpu->name);
36 printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
37 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
39 sw = CPLD_READ(flash_ctl_status);
40 sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
43 printf("vBank: %d\n", sw);
45 printf("Unsupported Bank=%x\n", sw);
50 int board_early_init_f(void)
52 #if defined(CONFIG_DEEP_SLEEP)
54 fsl_dp_disable_console();
60 int board_early_init_r(void)
62 #ifdef CONFIG_SYS_FLASH_BASE
63 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
64 int flash_esel = find_tlb_idx((void *)flashbase, 1);
67 * Remap Boot flash region to caching-inhibited
68 * so that flash can be erased properly.
71 /* Flush d-cache and invalidate i-cache of any FLASH data */
75 if (flash_esel == -1) {
76 /* very unlikely unless something is messed up */
77 puts("Error: Could not find TLB for FLASH BASE\n");
78 flash_esel = 2; /* give our best effort to continue */
80 /* invalidate existing TLB entry for flash */
81 disable_tlb(flash_esel);
84 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
85 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
86 0, flash_esel, BOOKE_PAGESZ_256M, 1);
89 #ifdef CONFIG_SYS_DPAA_QBMAN
98 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
101 srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
103 printf("SERDES Reference : 0x%X\n", srds_s1);
107 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
110 /* select SGMII and Aurora*/
112 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
113 MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
115 #if defined(CONFIG_T1040D4RDB)
116 /* Mask all CPLD interrupt sources, except QSGMII interrupts */
117 if (CPLD_READ(sw_ver) < 0x03) {
118 debug("CPLD SW version 0x%02x doesn't support int_mask\n",
121 CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
122 ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
129 int ft_board_setup(void *blob, bd_t *bd)
134 ft_cpu_setup(blob, bd);
136 base = getenv_bootm_low();
137 size = getenv_bootm_size();
139 fdt_fixup_memory(blob, (u64)base, (u64)size);
142 pci_of_setup(blob, bd);
145 fdt_fixup_liodn(blob);
147 #ifdef CONFIG_HAS_FSL_DR_USB
148 fdt_fixup_dr_usb(blob, bd);
151 #ifdef CONFIG_SYS_DPAA_FMAN
152 fdt_fixup_fman_ethernet(blob);