2 * Copyright (C) 2013 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/mxc_hdmi.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/sys_proto.h>
19 #include <asm/imx-common/iomux-v3.h>
20 #include <asm/imx-common/mxc_i2c.h>
21 #include <asm/imx-common/boot_mode.h>
22 #include <asm/imx-common/sata.h>
23 #include <asm/imx-common/video.h>
24 #include <jffs2/load_kernel.h>
27 #include <linux/ctype.h>
28 #include <fdt_support.h>
29 #include <fsl_esdhc.h>
34 #include <power/pmic.h>
35 #include <power/ltc3676_pmic.h>
36 #include <power/pfuze100_pmic.h>
37 #include <fdt_support.h>
38 #include <jffs2/load_kernel.h>
39 #include <spi_flash.h>
42 #include "ventana_eeprom.h"
44 DECLARE_GLOBAL_DATA_PTR;
46 /* GPIO's common to all baseboards */
47 #define GP_PHY_RST IMX_GPIO_NR(1, 30)
48 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
49 #define GP_SD3_CD IMX_GPIO_NR(7, 0)
50 #define GP_RS232_EN IMX_GPIO_NR(2, 11)
51 #define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
57 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
58 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
59 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
61 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
62 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
63 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
65 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
66 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
67 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
69 #define SPI_PAD_CTRL (PAD_CTL_HYS | \
70 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
71 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
73 #define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
74 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
75 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
77 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
78 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
79 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
81 #define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
82 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
83 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
85 #define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
89 * EEPROM board info struct populated by read_eeprom so that we only have to
92 static struct ventana_board_info ventana_info;
96 /* UART1: Function varies per baseboard */
97 iomux_v3_cfg_t const uart1_pads[] = {
98 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
99 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
102 /* UART2: Serial Console */
103 iomux_v3_cfg_t const uart2_pads[] = {
104 IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
105 IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
108 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
111 struct i2c_pads_info mx6q_i2c_pad_info0 = {
113 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
114 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
115 .gp = IMX_GPIO_NR(3, 21)
118 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
119 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
120 .gp = IMX_GPIO_NR(3, 28)
123 struct i2c_pads_info mx6dl_i2c_pad_info0 = {
125 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
126 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
127 .gp = IMX_GPIO_NR(3, 21)
130 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
131 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
132 .gp = IMX_GPIO_NR(3, 28)
136 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
137 struct i2c_pads_info mx6q_i2c_pad_info1 = {
139 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
140 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
141 .gp = IMX_GPIO_NR(4, 12)
144 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
145 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
146 .gp = IMX_GPIO_NR(4, 13)
149 struct i2c_pads_info mx6dl_i2c_pad_info1 = {
151 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
152 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
153 .gp = IMX_GPIO_NR(4, 12)
156 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
157 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
158 .gp = IMX_GPIO_NR(4, 13)
162 /* I2C3: Misc/Expansion */
163 struct i2c_pads_info mx6q_i2c_pad_info2 = {
165 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
166 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
167 .gp = IMX_GPIO_NR(1, 3)
170 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
171 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
172 .gp = IMX_GPIO_NR(1, 6)
175 struct i2c_pads_info mx6dl_i2c_pad_info2 = {
177 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
178 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
179 .gp = IMX_GPIO_NR(1, 3)
182 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
183 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
184 .gp = IMX_GPIO_NR(1, 6)
189 iomux_v3_cfg_t const usdhc3_pads[] = {
190 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
191 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
192 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
193 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
194 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
195 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
197 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
201 iomux_v3_cfg_t const enet_pads[] = {
202 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
203 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
204 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
205 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
206 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
207 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
208 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
209 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
210 MUX_PAD_CTRL(ENET_PAD_CTRL)),
211 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
212 MUX_PAD_CTRL(ENET_PAD_CTRL)),
213 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
214 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
215 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
216 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
217 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
218 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
219 MUX_PAD_CTRL(ENET_PAD_CTRL)),
221 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
225 iomux_v3_cfg_t const nfc_pads[] = {
226 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
227 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
228 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
229 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
230 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
231 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
232 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
233 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
234 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
235 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
236 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
237 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
238 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
239 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
240 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
243 #ifdef CONFIG_CMD_NAND
244 static void setup_gpmi_nand(void)
246 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
248 /* config gpmi nand iomux */
249 SETUP_IOMUX_PADS(nfc_pads);
251 /* config gpmi and bch clock to 100 MHz */
252 clrsetbits_le32(&mxc_ccm->cs2cdr,
253 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
254 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
255 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
256 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
257 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
258 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
260 /* enable gpmi and bch clock gating */
261 setbits_le32(&mxc_ccm->CCGR4,
262 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
263 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
264 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
265 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
266 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
268 /* enable apbh clock gating */
269 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
273 static void setup_iomux_enet(void)
275 SETUP_IOMUX_PADS(enet_pads);
277 /* toggle PHY_RST# */
278 gpio_direction_output(GP_PHY_RST, 0);
280 gpio_set_value(GP_PHY_RST, 1);
283 static void setup_iomux_uart(void)
285 SETUP_IOMUX_PADS(uart1_pads);
286 SETUP_IOMUX_PADS(uart2_pads);
289 #ifdef CONFIG_USB_EHCI_MX6
290 iomux_v3_cfg_t const usb_pads[] = {
291 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
292 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
294 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
297 int board_ehci_hcd_init(int port)
299 struct ventana_board_info *info = &ventana_info;
301 SETUP_IOMUX_PADS(usb_pads);
303 /* Reset USB HUB (present on GW54xx/GW53xx) */
304 switch (info->model[3]) {
305 case '3': /* GW53xx */
306 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
307 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
309 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
311 case '4': /* GW54xx */
312 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
313 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
315 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
322 int board_ehci_power(int port, int on)
326 gpio_set_value(GP_USB_OTG_PWR, on);
329 #endif /* CONFIG_USB_EHCI_MX6 */
331 #ifdef CONFIG_FSL_ESDHC
332 struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
334 int board_mmc_getcd(struct mmc *mmc)
337 gpio_direction_input(GP_SD3_CD);
338 return !gpio_get_value(GP_SD3_CD);
341 int board_mmc_init(bd_t *bis)
343 /* Only one USDHC controller on Ventana */
344 SETUP_IOMUX_PADS(usdhc3_pads);
345 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
346 usdhc_cfg.max_bus_width = 4;
348 return fsl_esdhc_initialize(bis, &usdhc_cfg);
350 #endif /* CONFIG_FSL_ESDHC */
352 #ifdef CONFIG_MXC_SPI
353 iomux_v3_cfg_t const ecspi1_pads[] = {
355 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
356 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
357 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
358 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
361 static void setup_spi(void)
363 gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
364 SETUP_IOMUX_PADS(ecspi1_pads);
368 /* configure eth0 PHY board-specific LED behavior */
369 int board_phy_config(struct phy_device *phydev)
374 if (phydev->phy_id == 0x1410dd1) {
376 * Page 3, Register 16: LED[2:0] Function Control Register
377 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
378 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
380 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
381 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
384 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
385 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
388 if (phydev->drv->config)
389 phydev->drv->config(phydev);
394 int board_eth_init(bd_t *bis)
398 #ifdef CONFIG_FEC_MXC
403 /* For otg ethernet*/
404 usb_eth_initialize(bis);
410 #if defined(CONFIG_VIDEO_IPUV3)
412 static void enable_hdmi(struct display_info_t const *dev)
414 imx_enable_hdmi_phy();
417 static int detect_i2c(struct display_info_t const *dev)
419 return i2c_set_bus_num(dev->bus) == 0 &&
420 i2c_probe(dev->addr) == 0;
423 static void enable_lvds(struct display_info_t const *dev)
425 struct iomuxc *iomux = (struct iomuxc *)
428 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
429 u32 reg = readl(&iomux->gpr[2]);
430 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
431 writel(reg, &iomux->gpr[2]);
433 /* Enable Backlight */
434 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
435 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
438 struct display_info_t const displays[] = {{
442 .pixfmt = IPU_PIX_FMT_RGB24,
443 .detect = detect_hdmi,
444 .enable = enable_hdmi,
458 .vmode = FB_VMODE_NONINTERLACED
460 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
463 .pixfmt = IPU_PIX_FMT_LVDS666,
464 .detect = detect_i2c,
465 .enable = enable_lvds,
467 .name = "Hannstar-XGA",
479 .vmode = FB_VMODE_NONINTERLACED
481 size_t display_count = ARRAY_SIZE(displays);
483 static void setup_display(void)
485 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
486 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
491 /* Turn on LDB0,IPU,IPU DI0 clocks */
492 reg = __raw_readl(&mxc_ccm->CCGR3);
493 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
494 writel(reg, &mxc_ccm->CCGR3);
496 /* set LDB0, LDB1 clk select to 011/011 */
497 reg = readl(&mxc_ccm->cs2cdr);
498 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
499 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
500 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
501 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
502 writel(reg, &mxc_ccm->cs2cdr);
504 reg = readl(&mxc_ccm->cscmr2);
505 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
506 writel(reg, &mxc_ccm->cscmr2);
508 reg = readl(&mxc_ccm->chsccdr);
509 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
510 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
511 writel(reg, &mxc_ccm->chsccdr);
513 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
514 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
515 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
516 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
517 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
518 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
519 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
520 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
521 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
522 writel(reg, &iomux->gpr[2]);
524 reg = readl(&iomux->gpr[3]);
525 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
526 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
527 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
528 writel(reg, &iomux->gpr[3]);
530 /* Backlight CABEN on LVDS connector */
531 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
532 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
534 #endif /* CONFIG_VIDEO_IPUV3 */
537 * Baseboard specific GPIO
540 /* common to add baseboards */
541 static iomux_v3_cfg_t const gw_gpio_pads[] = {
543 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
545 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
549 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
551 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
553 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
555 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
557 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
559 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
561 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
563 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
565 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
567 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
569 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
572 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
574 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
576 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
578 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
580 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
583 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
585 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
587 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
589 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
592 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
594 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
596 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
598 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
600 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
603 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
605 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
607 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
609 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
611 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
613 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
616 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
618 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
620 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
622 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
624 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
626 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
629 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
631 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
633 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
635 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
637 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
640 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
642 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
644 IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
646 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
648 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
650 IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
652 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
654 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
656 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
658 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
660 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
662 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
664 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
668 * each baseboard has 4 user configurable Digital IO lines which can
669 * be pinmuxed as a GPIO or in some cases a PWM
672 iomux_v3_cfg_t gpio_padmux[2];
674 iomux_v3_cfg_t pwm_padmux[2];
680 iomux_v3_cfg_t const *gpio_pads;
683 struct dio_cfg dio_cfg[4];
684 /* various gpios (0 if non-existent) */
698 struct ventana gpio_cfg[] = {
701 .gpio_pads = gw54xx_gpio_pads,
702 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
705 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
707 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
711 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
713 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
717 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
719 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
723 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
725 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
734 .pcie_rst = IMX_GPIO_NR(1, 29),
735 .mezz_pwren = IMX_GPIO_NR(4, 7),
736 .mezz_irq = IMX_GPIO_NR(4, 9),
737 .rs485en = IMX_GPIO_NR(3, 24),
738 .dioi2c_en = IMX_GPIO_NR(4, 5),
739 .pcie_sson = IMX_GPIO_NR(1, 20),
744 .gpio_pads = gw51xx_gpio_pads,
745 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
748 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
754 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
756 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
760 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
762 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
766 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
768 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
776 .pcie_rst = IMX_GPIO_NR(1, 0),
777 .mezz_pwren = IMX_GPIO_NR(2, 19),
778 .mezz_irq = IMX_GPIO_NR(2, 18),
779 .gps_shdn = IMX_GPIO_NR(1, 2),
780 .vidin_en = IMX_GPIO_NR(5, 20),
781 .wdis = IMX_GPIO_NR(7, 12),
786 .gpio_pads = gw52xx_gpio_pads,
787 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
790 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
796 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
798 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
802 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
804 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
808 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
819 .pcie_rst = IMX_GPIO_NR(1, 29),
820 .mezz_pwren = IMX_GPIO_NR(2, 19),
821 .mezz_irq = IMX_GPIO_NR(2, 18),
822 .gps_shdn = IMX_GPIO_NR(1, 27),
823 .vidin_en = IMX_GPIO_NR(3, 31),
824 .usb_sel = IMX_GPIO_NR(1, 2),
825 .wdis = IMX_GPIO_NR(7, 12),
830 .gpio_pads = gw53xx_gpio_pads,
831 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
834 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
840 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
842 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
846 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
848 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
852 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
863 .pcie_rst = IMX_GPIO_NR(1, 29),
864 .mezz_pwren = IMX_GPIO_NR(2, 19),
865 .mezz_irq = IMX_GPIO_NR(2, 18),
866 .gps_shdn = IMX_GPIO_NR(1, 27),
867 .vidin_en = IMX_GPIO_NR(3, 31),
868 .wdis = IMX_GPIO_NR(7, 12),
873 .gpio_pads = gw54xx_gpio_pads,
874 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
877 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
879 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
883 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
885 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
889 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
891 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
895 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
897 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
906 .pcie_rst = IMX_GPIO_NR(1, 29),
907 .mezz_pwren = IMX_GPIO_NR(2, 19),
908 .mezz_irq = IMX_GPIO_NR(2, 18),
909 .rs485en = IMX_GPIO_NR(7, 1),
910 .vidin_en = IMX_GPIO_NR(3, 31),
911 .dioi2c_en = IMX_GPIO_NR(4, 5),
912 .pcie_sson = IMX_GPIO_NR(1, 20),
913 .wdis = IMX_GPIO_NR(5, 17),
917 /* setup board specific PMIC */
918 int power_init_board(void)
923 /* configure PFUZE100 PMIC */
924 if (board_type == GW54xx || board_type == GW54proto) {
925 power_pfuze100_init(I2C_PMIC);
926 p = pmic_get("PFUZE100");
927 if (p && !pmic_probe(p)) {
928 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
929 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
931 /* Set VGEN1 to 1.5V and enable */
932 pmic_reg_read(p, PFUZE100_VGEN1VOL, ®);
933 reg &= ~(LDO_VOL_MASK);
934 reg |= (LDOA_1_50V | LDO_EN);
935 pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
937 /* Set SWBST to 5.0V and enable */
938 pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
939 reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
940 reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
941 pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
945 /* configure LTC3676 PMIC */
947 power_ltc3676_init(I2C_PMIC);
948 p = pmic_get("LTC3676_PMIC");
949 if (p && !pmic_probe(p)) {
950 puts("PMIC: LTC3676\n");
951 /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
952 if (is_cpu_type(MXC_CPU_MX6Q)) {
953 /* mask PGOOD during SW1 transition */
954 reg = 0x1d | LTC3676_PGOOD_MASK;
955 pmic_reg_write(p, LTC3676_DVB1B, reg);
956 /* set SW1 (VDD_SOC) to 1259mV */
958 pmic_reg_write(p, LTC3676_DVB1A, reg);
960 /* mask PGOOD during SW3 transition */
961 reg = 0x1d | LTC3676_PGOOD_MASK;
962 pmic_reg_write(p, LTC3676_DVB3B, reg);
963 /*set SW3 (VDD_ARM) to 1259mV */
965 pmic_reg_write(p, LTC3676_DVB3A, reg);
973 /* setup GPIO pinmux and default configuration per baseboard */
974 static void setup_board_gpio(int board)
976 struct ventana_board_info *info = &ventana_info;
981 int quiet = simple_strtol(getenv("quiet"), NULL, 10);
983 if (board >= GW_UNKNOWN)
987 gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
990 if (is_cpu_type(MXC_CPU_MX6Q) &&
991 test_bit(EECONFIG_SATA, info->config)) {
992 gpio_direction_output(GP_MSATA_SEL,
993 (hwconfig("msata")) ? 1 : 0);
995 gpio_direction_output(GP_MSATA_SEL, 0);
998 #if !defined(CONFIG_CMD_PCI)
999 /* assert PCI_RST# (released by OS when clock is valid) */
1000 gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
1003 /* turn off (active-high) user LED's */
1004 for (i = 0; i < 4; i++) {
1005 if (gpio_cfg[board].leds[i])
1006 gpio_direction_output(gpio_cfg[board].leds[i], 1);
1009 /* Expansion Mezzanine IO */
1010 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1011 gpio_direction_input(gpio_cfg[board].mezz_irq);
1013 /* RS485 Transmit Enable */
1014 if (gpio_cfg[board].rs485en)
1015 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1018 if (gpio_cfg[board].gps_shdn)
1019 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1021 /* Analog video codec power enable */
1022 if (gpio_cfg[board].vidin_en)
1023 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
1026 if (gpio_cfg[board].dioi2c_en)
1027 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1029 /* PCICK_SSON: disable spread-spectrum clock */
1030 if (gpio_cfg[board].pcie_sson)
1031 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1033 /* USBOTG Select (PCISKT or FrontPanel) */
1034 if (gpio_cfg[board].usb_sel)
1035 gpio_direction_output(gpio_cfg[board].usb_sel, 0);
1037 /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
1038 if (gpio_cfg[board].wdis)
1039 gpio_direction_output(gpio_cfg[board].wdis, 1);
1042 * Configure DIO pinmux/padctl registers
1043 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1045 for (i = 0; i < 4; i++) {
1046 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1047 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
1048 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1050 sprintf(arg, "dio%d", i);
1053 s = hwconfig_subarg(arg, "padctrl", &len);
1055 ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
1056 & 0x1ffff) | MUX_MODE_SION;
1058 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1060 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
1061 (cfg->gpio_param/32)+1,
1065 imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1067 gpio_direction_input(cfg->gpio_param);
1068 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1071 printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
1072 imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1073 MUX_PAD_CTRL(ctrl));
1078 if (is_cpu_type(MXC_CPU_MX6Q) &&
1079 (test_bit(EECONFIG_SATA, info->config))) {
1080 printf("MSATA: %s\n", (hwconfig("msata") ?
1081 "enabled" : "disabled"));
1083 printf("RS232: %s\n", (hwconfig("rs232")) ?
1084 "enabled" : "disabled");
1088 #if defined(CONFIG_CMD_PCI)
1089 int imx6_pcie_toggle_reset(void)
1091 if (board_type < GW_UNKNOWN) {
1092 uint pin = gpio_cfg[board_type].pcie_rst;
1093 gpio_direction_output(pin, 0);
1095 gpio_direction_output(pin, 1);
1099 #endif /* CONFIG_CMD_PCI */
1101 #ifdef CONFIG_SERIAL_TAG
1103 * called when setting up ATAGS before booting kernel
1104 * populate serialnum from the following (in order of priority):
1108 void get_board_serial(struct tag_serialnr *serialnr)
1110 char *serial = getenv("serial#");
1114 serialnr->low = simple_strtoul(serial, NULL, 10);
1115 } else if (ventana_info.model[0]) {
1117 serialnr->low = ventana_info.serial;
1129 /* called from SPL board_init_f() */
1130 int board_early_init_f(void)
1133 gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
1135 #if defined(CONFIG_VIDEO_IPUV3)
1143 gd->ram_size = imx_ddr_size();
1147 int board_init(void)
1149 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
1151 clrsetbits_le32(&iomuxc_regs->gpr[1],
1152 IOMUXC_GPR1_OTG_ID_MASK,
1153 IOMUXC_GPR1_OTG_ID_GPIO1);
1155 /* address of linux boot parameters */
1156 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1158 #ifdef CONFIG_CMD_NAND
1161 #ifdef CONFIG_MXC_SPI
1164 if (is_cpu_type(MXC_CPU_MX6Q)) {
1165 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
1166 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
1167 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
1169 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
1170 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
1171 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
1174 #ifdef CONFIG_CMD_SATA
1177 /* read Gateworks EEPROM into global struct (used later) */
1178 board_type = read_eeprom(I2C_GSC, &ventana_info);
1180 /* board-specifc GPIO iomux */
1181 SETUP_IOMUX_PADS(gw_gpio_pads);
1182 if (board_type < GW_UNKNOWN) {
1183 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
1184 int count = gpio_cfg[board_type].num_pads;
1186 imx_iomux_v3_setup_multiple_pads(p, count);
1192 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1194 * called during late init (after relocation and after board_init())
1195 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1198 int checkboard(void)
1200 struct ventana_board_info *info = &ventana_info;
1201 unsigned char buf[4];
1203 int quiet; /* Quiet or minimal output mode */
1206 p = getenv("quiet");
1208 quiet = simple_strtol(p, NULL, 10);
1210 setenv("quiet", "0");
1212 puts("\nGateworks Corporation Copyright 2014\n");
1213 if (info->model[0]) {
1214 printf("Model: %s\n", info->model);
1215 printf("MFGDate: %02x-%02x-%02x%02x\n",
1216 info->mfgdate[0], info->mfgdate[1],
1217 info->mfgdate[2], info->mfgdate[3]);
1218 printf("Serial:%d\n", info->serial);
1220 puts("Invalid EEPROM - board will not function fully\n");
1225 /* Display GSC firmware revision/CRC/status */
1226 i2c_set_bus_num(I2C_GSC);
1227 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
1228 printf("GSC: v%d", buf[0]);
1229 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
1230 printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
1231 printf(" 0x%02x", buf[0]); /* irq status */
1236 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1238 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1245 #ifdef CONFIG_CMD_BMODE
1247 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1248 * see Table 8-11 and Table 5-9
1249 * BOOT_CFG1[7] = 1 (boot from NAND)
1250 * BOOT_CFG1[5] = 0 - raw NAND
1251 * BOOT_CFG1[4] = 0 - default pad settings
1252 * BOOT_CFG1[3:2] = 00 - devices = 1
1253 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1254 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1255 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1256 * BOOT_CFG2[0] = 0 - Reset time 12ms
1258 static const struct boot_mode board_boot_modes[] = {
1259 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1260 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1266 int misc_init_r(void)
1268 struct ventana_board_info *info = &ventana_info;
1271 /* set env vars based on EEPROM data */
1272 if (ventana_info.model[0]) {
1273 char str[16], fdt[36];
1275 const char *cputype = "";
1279 * FDT name will be prefixed with CPU type. Three versions
1280 * will be created each increasingly generic and bootloader
1281 * env scripts will try loading each from most specific to
1284 if (is_cpu_type(MXC_CPU_MX6Q) ||
1285 is_cpu_type(MXC_CPU_MX6D))
1287 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1288 is_cpu_type(MXC_CPU_MX6SOLO))
1290 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
1291 setenv("flash_layout", "large");
1293 setenv("flash_layout", "normal");
1294 memset(str, 0, sizeof(str));
1295 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1296 str[i] = tolower(info->model[i]);
1297 if (!getenv("model"))
1298 setenv("model", str);
1299 if (!getenv("fdt_file")) {
1300 sprintf(fdt, "%s-%s.dtb", cputype, str);
1301 setenv("fdt_file", fdt);
1303 p = strchr(str, '-');
1307 setenv("model_base", str);
1308 if (!getenv("fdt_file1")) {
1309 sprintf(fdt, "%s-%s.dtb", cputype, str);
1310 setenv("fdt_file1", fdt);
1315 if (!getenv("fdt_file2")) {
1316 sprintf(fdt, "%s-%s.dtb", cputype, str);
1317 setenv("fdt_file2", fdt);
1321 /* initialize env from EEPROM */
1322 if (test_bit(EECONFIG_ETH0, info->config) &&
1323 !getenv("ethaddr")) {
1324 eth_setenv_enetaddr("ethaddr", info->mac0);
1326 if (test_bit(EECONFIG_ETH1, info->config) &&
1327 !getenv("eth1addr")) {
1328 eth_setenv_enetaddr("eth1addr", info->mac1);
1331 /* board serial-number */
1332 sprintf(str, "%6d", info->serial);
1333 setenv("serial#", str);
1337 /* setup baseboard specific GPIO pinmux and config */
1338 setup_board_gpio(board_type);
1340 #ifdef CONFIG_CMD_BMODE
1341 add_board_boot_modes(board_boot_modes);
1345 * The Gateworks System Controller implements a boot
1346 * watchdog (always enabled) as a workaround for IMX6 boot related
1348 * ERR005768 - no fix
1349 * ERR006282 - fixed in silicon r1.3
1350 * ERR007117 - fixed in silicon r1.3
1351 * ERR007220 - fixed in silicon r1.3
1352 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1354 * Disable the boot watchdog and display/clear the timeout flag if set
1356 i2c_set_bus_num(I2C_GSC);
1357 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) {
1358 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1359 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
1360 puts("Error: could not disable GSC Watchdog\n");
1362 puts("Error: could not disable GSC Watchdog\n");
1364 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) {
1365 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
1366 puts("GSC boot watchdog timeout detected\n");
1367 reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
1368 gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1);
1375 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1377 /* FDT aliases associated with EEPROM config bits */
1378 const char *fdt_aliases[] = {
1446 * called prior to booting kernel or by 'fdt boardsetup' command
1448 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1449 * - mtd partitions based on mtdparts/mtdids env
1450 * - system-serial (board serial num from EEPROM)
1451 * - board (full model from EEPROM)
1452 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1454 void ft_board_setup(void *blob, bd_t *bd)
1457 struct ventana_board_info *info = &ventana_info;
1458 struct node_info nodes[] = {
1459 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1460 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1462 const char *model = getenv("model");
1464 if (getenv("fdt_noauto")) {
1465 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1469 /* Update partition nodes using info from mtdparts env var */
1470 puts(" Updating MTD partitions...\n");
1471 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1474 puts("invalid board info: Leaving FDT fully enabled\n");
1477 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1479 /* board serial number */
1480 fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1481 strlen(getenv("serial#")) + 1);
1483 /* board (model contains model from device-tree) */
1484 fdt_setprop(blob, 0, "board", info->model,
1485 strlen((const char *)info->model) + 1);
1488 * Peripheral Config:
1489 * remove nodes by alias path if EEPROM config tells us the
1490 * peripheral is not loaded on the board.
1492 for (bit = 0; bit < 64; bit++) {
1493 if (!test_bit(bit, info->config))
1494 fdt_del_node_and_alias(blob, fdt_aliases[bit]);
1497 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */