3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/ppc4xx-gpio.h>
16 #include <gdsys_fpga.h>
18 #include "../common/osd.h"
20 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
21 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
22 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
23 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
25 #define LATCH2_MC2_PRESENT_N 0x0080
29 UNITTYPE_SERVER = 1<<1,
30 UNITTYPE_DISPLAYPORT = 1<<2,
60 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
70 static unsigned int get_hwver(void)
72 u16 latch3 = in_le16((void *)LATCH3_BASE);
74 return latch3 & 0x0003;
77 static unsigned int get_mc2_present(void)
79 u16 latch2 = in_le16((void *)LATCH2_BASE);
81 return !(latch2 & LATCH2_MC2_PRESENT_N);
84 static void print_fpga_info(unsigned dev)
90 unsigned hardware_version;
91 unsigned feature_rs232;
92 unsigned feature_audio;
93 unsigned feature_sysclock;
94 unsigned feature_ramconfig;
95 unsigned feature_carrier_speed;
96 unsigned feature_carriers;
97 unsigned feature_video_channels;
98 int fpga_state = get_fpga_state(dev);
100 printf("FPGA%d: ", dev);
102 FPGA_GET_REG(dev, versions, &versions);
103 FPGA_GET_REG(dev, fpga_version, &fpga_version);
104 FPGA_GET_REG(dev, fpga_features, &fpga_features);
106 hardware_version = versions & 0x000f;
109 && !((hardware_version == HWVER_101)
110 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
111 puts("not available\n");
112 print_fpga_state(dev);
116 unit_type = (versions >> 4) & 0x000f;
117 hardware_version = versions & 0x000f;
118 feature_rs232 = fpga_features & (1<<11);
119 feature_audio = (fpga_features >> 9) & 0x0003;
120 feature_sysclock = (fpga_features >> 7) & 0x0003;
121 feature_ramconfig = (fpga_features >> 5) & 0x0003;
122 feature_carrier_speed = fpga_features & (1<<4);
123 feature_carriers = (fpga_features >> 2) & 0x0003;
124 feature_video_channels = fpga_features & 0x0003;
126 if (unit_type & UNITTYPE_MAIN)
127 printf("Mainchannel ");
129 printf("Videochannel ");
131 if (unit_type & UNITTYPE_SERVER)
132 printf("Serverside ");
136 if (unit_type & UNITTYPE_DISPLAYPORT)
137 printf("DisplayPort");
141 switch (hardware_version) {
143 printf(" HW-Ver 1.01\n");
147 printf(" HW-Ver 1.10-1.20\n");
151 printf(" HW-Ver 1.30\n");
155 printf(" HW-Ver 1.40-1.43\n");
159 printf(" HW-Ver 1.50\n");
163 printf(" HW-Ver 1.60-1.61\n");
167 printf(" HW-Ver 1.70\n");
171 printf(" HW-Ver %d(not supported)\n",
176 printf(" FPGA V %d.%02d, features:",
177 fpga_version / 100, fpga_version % 100);
179 printf(" %sRS232", feature_rs232 ? "" : "no ");
181 switch (feature_audio) {
183 printf(", no audio");
187 printf(", audio tx");
191 printf(", audio rx");
195 printf(", audio rx+tx");
199 printf(", audio %d(not supported)", feature_audio);
203 switch (feature_sysclock) {
205 printf(", clock 156.25 MHz");
209 printf(", clock %d(not supported)", feature_sysclock);
215 switch (feature_ramconfig) {
221 printf("RAM 32 bit DDR2");
225 printf("RAM 64 bit DDR2");
229 printf("RAM %d(not supported)", feature_ramconfig);
233 printf(", %d carrier(s) %s", feature_carriers,
234 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
236 printf(", %d video channel(s)\n", feature_video_channels);
240 * Check Board Identity:
244 char *s = getenv("serial#");
248 puts("DLVision 10G");
260 int last_stage_init(void)
264 FPGA_GET_REG(0, versions, &versions);
267 if (get_mc2_present())
270 if (((versions >> 4) & 0x000f) & UNITTYPE_SERVER)
273 if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
276 if (get_mc2_present() &&
277 (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
283 void gd405ep_init(void)
287 void gd405ep_set_fpga_reset(unsigned state)
290 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
291 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
293 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
294 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
298 void gd405ep_setup_hw(void)
301 * set "startup-finished"-gpios
303 gpio_write_bit(21, 0);
304 gpio_write_bit(22, 1);
307 int gd405ep_get_fpga_done(unsigned fpga)
309 return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);