3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/ppc4xx-gpio.h>
31 #include <gdsys_fpga.h>
33 #include "../common/osd.h"
35 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
36 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
37 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
38 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
40 #define LATCH2_MC2_PRESENT_N 0x0080
43 UNITTYPE_VIDEO_USER = 0,
44 UNITTYPE_MAIN_USER = 1,
45 UNITTYPE_VIDEO_SERVER = 2,
46 UNITTYPE_MAIN_SERVER = 3,
71 static unsigned int get_hwver(void)
73 u16 latch3 = in_le16((void *)LATCH3_BASE);
75 return latch3 & 0x0003;
78 static unsigned int get_mc2_present(void)
80 u16 latch2 = in_le16((void *)LATCH2_BASE);
82 return !(latch2 & LATCH2_MC2_PRESENT_N);
85 static void print_fpga_info(unsigned dev)
87 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
88 u16 versions = in_le16(&fpga->versions);
89 u16 fpga_version = in_le16(&fpga->fpga_version);
90 u16 fpga_features = in_le16(&fpga->fpga_features);
92 unsigned hardware_version;
93 unsigned feature_rs232;
94 unsigned feature_audio;
95 unsigned feature_sysclock;
96 unsigned feature_ramconfig;
97 unsigned feature_carrier_speed;
98 unsigned feature_carriers;
99 unsigned feature_video_channels;
100 int fpga_state = get_fpga_state(dev);
102 printf("FPGA%d: ", dev);
104 hardware_version = versions & 0x000f;
107 && !((hardware_version == HWVER_101)
108 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
109 puts("not available\n");
110 print_fpga_state(dev);
114 unit_type = (versions >> 4) & 0x000f;
115 hardware_version = versions & 0x000f;
116 feature_rs232 = fpga_features & (1<<11);
117 feature_audio = (fpga_features >> 9) & 0x0003;
118 feature_sysclock = (fpga_features >> 7) & 0x0003;
119 feature_ramconfig = (fpga_features >> 5) & 0x0003;
120 feature_carrier_speed = fpga_features & (1<<4);
121 feature_carriers = (fpga_features >> 2) & 0x0003;
122 feature_video_channels = fpga_features & 0x0003;
125 case UNITTYPE_VIDEO_USER:
126 printf("Videochannel Userside");
129 case UNITTYPE_MAIN_USER:
130 printf("Mainchannel Userside");
133 case UNITTYPE_VIDEO_SERVER:
134 printf("Videochannel Serverside");
137 case UNITTYPE_MAIN_SERVER:
138 printf("Mainchannel Serverside");
142 printf("UnitType %d(not supported)", unit_type);
146 switch (hardware_version) {
148 printf(" HW-Ver 1.01\n");
152 printf(" HW-Ver 1.10\n");
156 printf(" HW-Ver %d(not supported)\n",
161 printf(" FPGA V %d.%02d, features:",
162 fpga_version / 100, fpga_version % 100);
164 printf(" %sRS232", feature_rs232 ? "" : "no ");
166 switch (feature_audio) {
168 printf(", no audio");
172 printf(", audio tx");
176 printf(", audio rx");
180 printf(", audio rx+tx");
184 printf(", audio %d(not supported)", feature_audio);
188 switch (feature_sysclock) {
190 printf(", clock 156.25 MHz");
194 printf(", clock %d(not supported)", feature_sysclock);
200 switch (feature_ramconfig) {
206 printf("RAM 32 bit DDR2");
210 printf("RAM 64 bit DDR2");
214 printf("RAM %d(not supported)", feature_ramconfig);
218 printf(", %d carrier(s) %s", feature_carriers,
219 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
221 printf(", %d video channel(s)\n", feature_video_channels);
225 * Check Board Identity:
230 int i = getenv_f("serial#", buf, sizeof(buf));
234 printf("DLVision 10G");
244 if (get_mc2_present())
250 int last_stage_init(void)
252 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
253 u16 versions = in_le16(&fpga->versions);
255 if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
258 if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
261 if (get_mc2_present() &&
262 (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
268 void gd405ep_init(void)
272 void gd405ep_set_fpga_reset(unsigned state)
275 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
276 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
278 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
279 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
283 void gd405ep_setup_hw(void)
286 * set "startup-finished"-gpios
288 gpio_write_bit(21, 0);
289 gpio_write_bit(22, 1);
292 int gd405ep_get_fpga_done(unsigned fpga)
294 return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);