3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
6 * by Stefan Roese, DENX Software Engineering, sr@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/ppc4xx.h>
29 #include <asm/ppc405.h>
31 #include <fdt_support.h>
32 #include <asm/processor.h>
34 #include <asm/errno.h>
35 #include <asm/ppc4xx-gpio.h>
41 #include <gdsys_fpga.h>
47 DECLARE_GLOBAL_DATA_PTR;
49 #define PHYREG_CONTROL 0
50 #define PHYREG_PAGE_ADDRESS 22
51 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
52 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
53 #define PHYREG_PG2_MAC_SPECIFIC_STATUS_1 17
54 #define PHYREG_PG2_MAC_SPECIFIC_CONTROL 21
56 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
57 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
58 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
59 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
62 UNITTYPE_CCD_SWITCH = 1,
70 static inline void blank_string(int size)
74 for (i = 0; i < size; i++)
76 for (i = 0; i < size; i++)
78 for (i = 0; i < size; i++)
83 * Board early initialization function
90 #ifdef CONFIG_ENV_IS_IN_FLASH
91 /* Monitor protection ON by default */
92 flash_protect(FLAG_PROTECT_SET,
93 -CONFIG_SYS_MONITOR_LEN,
101 static void print_fpga_info(unsigned dev)
103 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
104 u16 versions = in_le16(&fpga->versions);
105 u16 fpga_version = in_le16(&fpga->fpga_version);
106 u16 fpga_features = in_le16(&fpga->fpga_features);
107 int fpga_state = get_fpga_state(dev);
110 unsigned hardware_version;
111 unsigned feature_channels;
112 unsigned feature_expansion;
114 printf("FPGA%d: ", dev);
115 if (fpga_state & FPGA_STATE_PLATFORM)
118 if (fpga_state & FPGA_STATE_DONE_FAILED) {
119 printf(" done timed out\n");
123 if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
124 printf(" refelectione test failed\n");
128 unit_type = (versions & 0xf000) >> 12;
129 hardware_version = versions & 0x000f;
130 feature_channels = fpga_features & 0x007f;
131 feature_expansion = fpga_features & (1<<15);
134 case UNITTYPE_CCD_SWITCH:
135 printf("CCD-Switch");
139 printf("UnitType %d(not supported)", unit_type);
143 switch (hardware_version) {
145 printf(" HW-Ver 1.00\n");
149 printf(" HW-Ver 1.10\n");
153 printf(" HW-Ver %d(not supported)\n",
158 printf(" FPGA V %d.%02d, features:",
159 fpga_version / 100, fpga_version % 100);
161 printf(" %d channel(s)", feature_channels);
163 printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
168 char *s = getenv("serial#");
170 printf("Board: CATCenter Io64\n");
180 int configure_gbit_phy(char *bus, unsigned char addr)
182 unsigned short value;
185 if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
187 /* switch to powerdown */
188 if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
191 if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
195 if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
197 /* disable SGMII autonegotiation */
198 if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48))
201 if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
203 /* switch from powerdown to normal operation */
204 if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
207 if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
210 /* reset phy so settings take effect */
211 if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140))
217 printf("Error writing to the PHY addr=%02x\n", addr);
221 int verify_gbit_phy(char *bus, unsigned char addr)
223 unsigned short value;
226 if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
228 /* verify SGMII link status */
229 if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value))
231 if (!(value & (1 << 10)))
237 printf("Error writing to the PHY addr=%02x\n", addr);
241 int last_stage_init(void)
245 ihs_fpga_t *fpga0 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
246 ihs_fpga_t *fpga1 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(1);
248 char str_phys[] = "Setup PHYs -";
249 char str_serdes[] = "Start SERDES blocks";
250 char str_channels[] = "Start FPGA channels";
251 char str_locks[] = "Verify SERDES locks";
252 char str_status[] = "Verify PHY status -";
253 char slash[] = "\\|/-\\|/-";
258 /* setup Gbit PHYs */
261 miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
262 bb_miiphy_read, bb_miiphy_write);
264 for (k = 0; k < 32; ++k) {
265 configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k);
270 miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME,
271 bb_miiphy_read, bb_miiphy_write);
273 for (k = 0; k < 32; ++k) {
274 configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k);
278 blank_string(strlen(str_phys));
280 /* take fpga serdes blocks out of reset */
283 out_le16(&fpga0->quad_serdes_reset, 0);
284 out_le16(&fpga1->quad_serdes_reset, 0);
285 blank_string(strlen(str_serdes));
287 /* take channels out of reset */
290 for (fpga = 0; fpga < 2; ++fpga) {
291 u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int;
292 for (k = 0; k < 32; ++k)
293 out_le16(ch0_config_int + 4 * k, 0);
295 blank_string(strlen(str_channels));
297 /* verify channels serdes lock */
300 for (fpga = 0; fpga < 2; ++fpga) {
301 u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int;
302 for (k = 0; k < 32; ++k) {
303 u16 status = in_le16(ch0_status_int + 4*k);
304 if (!(status & (1 << 4))) {
306 printf("fpga %d channel %d: no serdes lock\n",
310 out_le16(ch0_status_int + 4*k, status);
313 blank_string(strlen(str_locks));
315 /* verify phy status */
317 for (k = 0; k < 32; ++k) {
318 if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) {
319 printf("verify baseboard phy %d failed\n", k);
325 for (k = 0; k < 32; ++k) {
326 if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) {
327 printf("verify extensionboard phy %d failed\n", k);
333 blank_string(strlen(str_status));
335 printf("Starting 64 channels %s\n", failed ? "failed" : "ok");
340 void gd405ex_init(void)
344 if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
345 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
346 gd->fpga_state[k] |= FPGA_STATE_PLATFORM;
348 pca9698_direction_output(0x22, 39, 1);
352 void gd405ex_set_fpga_reset(unsigned state)
354 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
358 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
359 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
361 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
362 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
365 pca9698_set_value(0x22, 39, state ? 0 : 1);
369 void gd405ex_setup_hw(void)
371 gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0);
372 gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1);
375 int gd405ex_get_fpga_done(unsigned fpga)
377 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
380 return in_le16((void *)LATCH3_BASE)
381 & CONFIG_SYS_FPGA_DONE(fpga);
383 return pca9698_get_value(0x22, fpga ? 9 : 8);