3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <gdsys_fpga.h>
14 #define CH7301_I2C_ADDR 0x75
16 #define ICS8N3QV01_I2C_ADDR 0x6E
17 #define ICS8N3QV01_FREF 114285000
18 #define ICS8N3QV01_FREF_LL 114285000LL
19 #define ICS8N3QV01_F_DEFAULT_0 156250000LL
20 #define ICS8N3QV01_F_DEFAULT_1 125000000LL
21 #define ICS8N3QV01_F_DEFAULT_2 100000000LL
22 #define ICS8N3QV01_F_DEFAULT_3 25175000LL
24 #define SIL1178_MASTER_I2C_ADDRESS 0x38
25 #define SIL1178_SLAVE_I2C_ADDRESS 0x39
27 #define PIXCLK_640_480_60 25180000
30 CH7301_CM = 0x1c, /* Clock Mode Register */
31 CH7301_IC = 0x1d, /* Input Clock Register */
32 CH7301_GPIO = 0x1e, /* GPIO Control Register */
33 CH7301_IDF = 0x1f, /* Input Data Format Register */
34 CH7301_CD = 0x20, /* Connection Detect Register */
35 CH7301_DC = 0x21, /* DAC Control Register */
36 CH7301_HPD = 0x23, /* Hot Plug Detection Register */
37 CH7301_TCTL = 0x31, /* DVI Control Input Register */
38 CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
39 CH7301_TPD = 0x34, /* DVI PLL Divide Register */
40 CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
41 CH7301_TPF = 0x36, /* DVI PLL Filter Register */
42 CH7301_TCT = 0x37, /* DVI Clock Test Register */
43 CH7301_TSTP = 0x48, /* Test Pattern Register */
44 CH7301_PM = 0x49, /* Power Management register */
45 CH7301_VID = 0x4a, /* Version ID Register */
46 CH7301_DID = 0x4b, /* Device ID Register */
47 CH7301_DSP = 0x56, /* DVI Sync polarity Register */
50 unsigned int base_width;
51 unsigned int base_height;
55 unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
57 #ifdef CONFIG_SYS_CH7301
58 int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
61 #if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
62 static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
67 FPGA_GET_REG(screen, extended_interrupt, &val);
68 } while (val & (1 << 12));
70 FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8));
71 FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1));
74 static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
80 FPGA_GET_REG(screen, extended_interrupt, &val);
81 } while (val & (1 << 12));
83 FPGA_SET_REG(screen, extended_interrupt, 1 << 14);
84 FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg);
85 FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1));
87 FPGA_GET_REG(screen, extended_interrupt, &val);
88 while (!(val & (1 << 14))) {
91 printf("iic receive timeout\n");
94 FPGA_GET_REG(screen, extended_interrupt, &val);
97 FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val);
102 #ifdef CONFIG_SYS_MPC92469AC
103 static void mpc92469ac_calc_parameters(unsigned int fout,
104 unsigned int *post_div, unsigned int *feedback_div)
106 unsigned int n = *post_div;
107 unsigned int m = *feedback_div;
109 unsigned int b = 14745600 / 16;
113 else if (fout < 100339199)
115 else if (fout < 200678399)
120 a = fout * n + (b / 2); /* add b/2 for proper rounding */
128 static void mpc92469ac_set(unsigned screen, unsigned int fout)
132 unsigned int bitval = 0;
133 mpc92469ac_calc_parameters(fout, &n, &m);
150 FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m);
154 #ifdef CONFIG_SYS_ICS8N3QV01
156 static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index)
158 unsigned long long n;
159 unsigned long long mint;
160 unsigned long long mfrac;
161 u8 reg_a, reg_b, reg_c, reg_d, reg_f;
162 unsigned long long fout_calc;
167 reg_a = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0 + index);
168 reg_b = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 4 + index);
169 reg_c = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 8 + index);
170 reg_d = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 12 + index);
171 reg_f = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20 + index);
173 mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
174 mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
178 fout_calc = (mint * ICS8N3QV01_FREF_LL
179 + mfrac * ICS8N3QV01_FREF_LL / 262144LL
180 + ICS8N3QV01_FREF_LL / 524288LL
190 static void ics8n3qv01_calc_parameters(unsigned int fout,
191 unsigned int *_mint, unsigned int *_mfrac,
195 unsigned int foutiic;
196 unsigned int fvcoiic;
198 unsigned long long mfrac;
200 n = (2215000000U + fout / 2) / fout;
201 if ((n & 1) && (n > 5))
204 foutiic = fout - (fout / 10000);
205 fvcoiic = foutiic * n;
207 mint = fvcoiic / 114285000;
208 if ((mint < 17) || (mint > 63))
209 printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
211 mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
219 static void ics8n3qv01_set(unsigned screen, unsigned int fout)
224 unsigned int fout_calc;
225 unsigned long long fout_prog;
227 u8 reg0, reg4, reg8, reg12, reg18, reg20;
229 fout_calc = ics8n3qv01_get_fout_calc(screen, 1);
230 off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
231 / ICS8N3QV01_F_DEFAULT_1;
232 printf(" PLL is off by %lld ppm\n", off_ppm);
233 fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc
234 / ICS8N3QV01_F_DEFAULT_1;
235 ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
237 reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
238 reg0 |= (mint & 0x1f) << 1;
239 reg0 |= (mfrac >> 17) & 0x01;
240 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0);
243 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4);
246 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8);
250 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12);
252 reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03;
254 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18);
256 reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
257 reg20 |= mint & (1 << 5);
258 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20);
262 static int osd_write_videomem(unsigned screen, unsigned offset,
263 u16 *data, size_t charcount)
267 for (k = 0; k < charcount; ++k) {
268 if (offset + k >= bufsize)
270 FPGA_SET_REG(screen, videomem[offset + k], data[k]);
276 static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
280 for (screen = 0; screen <= max_osd_screen; ++screen) {
295 x = simple_strtoul(argv[1], NULL, 16);
296 y = simple_strtoul(argv[2], NULL, 16);
297 color = simple_strtoul(argv[3], NULL, 16);
299 charcount = strlen(text);
300 len = (charcount > bufsize) ? bufsize : charcount;
302 for (k = 0; k < len; ++k)
303 buf[k] = (text[k] << 8) | color;
305 res = osd_write_videomem(screen, y * base_width + x, buf, len);
313 int osd_probe(unsigned screen)
318 #ifdef CONFIG_SYS_CH7301
319 int old_bus = i2c_get_bus_num();
322 FPGA_GET_REG(0, osd.version, &version);
323 FPGA_GET_REG(0, osd.features, &features);
325 base_width = ((features & 0x3f00) >> 8) + 1;
326 base_height = (features & 0x001f) + 1;
327 bufsize = base_width * base_height;
328 buf = malloc(sizeof(u16) * bufsize);
332 printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
333 screen, version/100, version%100, base_width, base_height);
335 #ifdef CONFIG_SYS_CH7301
336 i2c_set_bus_num(ch7301_i2c[screen]);
337 value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
339 printf(" Probing CH7301 failed, DID %02x\n", value);
340 i2c_set_bus_num(old_bus);
343 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
344 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
345 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
346 i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
347 i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
348 i2c_set_bus_num(old_bus);
351 #ifdef CONFIG_SYS_MPC92469AC
352 mpc92469ac_set(screen, PIXCLK_640_480_60);
355 #ifdef CONFIG_SYS_ICS8N3QV01
356 ics8n3qv01_set(screen, PIXCLK_640_480_60);
359 #ifdef CONFIG_SYS_SIL1178
360 value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02);
362 printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value);
365 /* magic initialization sequence adapted from datasheet */
366 fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
367 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
368 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
369 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
370 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
371 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
372 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
373 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
374 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
375 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
378 FPGA_SET_REG(screen, videocontrol, 0x0002);
379 FPGA_SET_REG(screen, osd.control, 0x0049);
381 FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
382 FPGA_SET_REG(screen, osd.x_pos, 0x007f);
383 FPGA_SET_REG(screen, osd.y_pos, 0x005f);
385 if (screen > max_osd_screen)
386 max_osd_screen = screen;
391 int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
395 for (screen = 0; screen <= max_osd_screen; ++screen) {
399 u16 buffer[base_width];
402 unsigned count = (argc > 4) ?
403 simple_strtoul(argv[4], NULL, 16) : 1;
405 if ((argc < 4) || (strlen(argv[3]) % 4)) {
410 x = simple_strtoul(argv[1], NULL, 16);
411 y = simple_strtoul(argv[2], NULL, 16);
418 memcpy(substr, rp, 4);
420 *wp = simple_strtoul(substr, NULL, 16);
424 if (wp - buffer > base_width)
428 for (k = 0; k < count; ++k) {
430 y * base_width + x + k * (wp - buffer);
431 osd_write_videomem(screen, offset, buffer,
440 osdw, 5, 0, osd_write,
441 "write 16-bit hex encoded buffer to osd memory",
442 "pos_x pos_y buffer count\n"
446 osdp, 5, 0, osd_print,
447 "write ASCII buffer to osd memory",
448 "pos_x pos_y color text\n"