3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <gdsys_fpga.h>
14 #define CH7301_I2C_ADDR 0x75
16 #define ICS8N3QV01_I2C_ADDR 0x6E
17 #define ICS8N3QV01_FREF 114285000
18 #define ICS8N3QV01_FREF_LL 114285000LL
19 #define ICS8N3QV01_F_DEFAULT_0 156250000LL
20 #define ICS8N3QV01_F_DEFAULT_1 125000000LL
21 #define ICS8N3QV01_F_DEFAULT_2 100000000LL
22 #define ICS8N3QV01_F_DEFAULT_3 25175000LL
24 #define SIL1178_MASTER_I2C_ADDRESS 0x38
25 #define SIL1178_SLAVE_I2C_ADDRESS 0x39
27 #define PIXCLK_640_480_60 25180000
30 #define BASE_HEIGHT 16
31 #define BUFSIZE (BASE_WIDTH * BASE_HEIGHT)
34 CH7301_CM = 0x1c, /* Clock Mode Register */
35 CH7301_IC = 0x1d, /* Input Clock Register */
36 CH7301_GPIO = 0x1e, /* GPIO Control Register */
37 CH7301_IDF = 0x1f, /* Input Data Format Register */
38 CH7301_CD = 0x20, /* Connection Detect Register */
39 CH7301_DC = 0x21, /* DAC Control Register */
40 CH7301_HPD = 0x23, /* Hot Plug Detection Register */
41 CH7301_TCTL = 0x31, /* DVI Control Input Register */
42 CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
43 CH7301_TPD = 0x34, /* DVI PLL Divide Register */
44 CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
45 CH7301_TPF = 0x36, /* DVI PLL Filter Register */
46 CH7301_TCT = 0x37, /* DVI Clock Test Register */
47 CH7301_TSTP = 0x48, /* Test Pattern Register */
48 CH7301_PM = 0x49, /* Power Management register */
49 CH7301_VID = 0x4a, /* Version ID Register */
50 CH7301_DID = 0x4b, /* Device ID Register */
51 CH7301_DSP = 0x56, /* DVI Sync polarity Register */
54 #if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
55 static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
57 struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
58 struct ihs_i2c *i2c = &fpga->i2c;
60 while (in_le16(&fpga->extended_interrupt) & (1 << 12))
62 out_le16(&i2c->write_mailbox_ext, reg | (data << 8));
63 out_le16(&i2c->write_mailbox, 0xc400 | (slave << 1));
66 static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
68 struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
69 struct ihs_i2c *i2c = &fpga->i2c;
72 while (in_le16(&fpga->extended_interrupt) & (1 << 12))
74 out_le16(&fpga->extended_interrupt, 1 << 14);
75 out_le16(&i2c->write_mailbox_ext, reg);
76 out_le16(&i2c->write_mailbox, 0xc000 | (slave << 1));
77 while (!(in_le16(&fpga->extended_interrupt) & (1 << 14))) {
80 printf("iic receive timeout\n");
84 return in_le16(&i2c->read_mailbox_ext) >> 8;
88 #ifdef CONFIG_SYS_MPC92469AC
89 static void mpc92469ac_calc_parameters(unsigned int fout,
90 unsigned int *post_div, unsigned int *feedback_div)
92 unsigned int n = *post_div;
93 unsigned int m = *feedback_div;
95 unsigned int b = 14745600 / 16;
99 else if (fout < 100339199)
101 else if (fout < 200678399)
106 a = fout * n + (b / 2); /* add b/2 for proper rounding */
114 static void mpc92469ac_set(unsigned screen, unsigned int fout)
116 struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
119 unsigned int bitval = 0;
120 mpc92469ac_calc_parameters(fout, &n, &m);
137 out_le16(&fpga->mpc3w_control, (bitval << 9) | m);
141 #ifdef CONFIG_SYS_ICS8N3QV01
143 static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index)
145 unsigned long long n;
146 unsigned long long mint;
147 unsigned long long mfrac;
148 u8 reg_a, reg_b, reg_c, reg_d, reg_f;
149 unsigned long long fout_calc;
154 reg_a = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0 + index);
155 reg_b = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 4 + index);
156 reg_c = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 8 + index);
157 reg_d = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 12 + index);
158 reg_f = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20 + index);
160 mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
161 mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
165 fout_calc = (mint * ICS8N3QV01_FREF_LL
166 + mfrac * ICS8N3QV01_FREF_LL / 262144LL
167 + ICS8N3QV01_FREF_LL / 524288LL
177 static void ics8n3qv01_calc_parameters(unsigned int fout,
178 unsigned int *_mint, unsigned int *_mfrac,
182 unsigned int foutiic;
183 unsigned int fvcoiic;
185 unsigned long long mfrac;
187 n = (2215000000U + fout / 2) / fout;
188 if ((n & 1) && (n > 5))
191 foutiic = fout - (fout / 10000);
192 fvcoiic = foutiic * n;
194 mint = fvcoiic / 114285000;
195 if ((mint < 17) || (mint > 63))
196 printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
198 mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
206 static void ics8n3qv01_set(unsigned screen, unsigned int fout)
211 unsigned int fout_calc;
212 unsigned long long fout_prog;
214 u8 reg0, reg4, reg8, reg12, reg18, reg20;
216 fout_calc = ics8n3qv01_get_fout_calc(screen, 1);
217 off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
218 / ICS8N3QV01_F_DEFAULT_1;
219 printf(" PLL is off by %lld ppm\n", off_ppm);
220 fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc
221 / ICS8N3QV01_F_DEFAULT_1;
222 ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
224 reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
225 reg0 |= (mint & 0x1f) << 1;
226 reg0 |= (mfrac >> 17) & 0x01;
227 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0);
230 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4);
233 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8);
237 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12);
239 reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03;
241 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18);
243 reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
244 reg20 |= mint & (1 << 5);
245 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20);
249 static int osd_write_videomem(unsigned screen, unsigned offset,
250 u16 *data, size_t charcount)
252 struct ihs_fpga *fpga =
253 (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(screen);
256 for (k = 0; k < charcount; ++k) {
257 if (offset + k >= BUFSIZE)
259 out_le16(&fpga->videomem + offset + k, data[k]);
265 static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
269 for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
285 x = simple_strtoul(argv[1], NULL, 16);
286 y = simple_strtoul(argv[2], NULL, 16);
287 color = simple_strtoul(argv[3], NULL, 16);
289 charcount = strlen(text);
290 len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
292 for (k = 0; k < len; ++k)
293 buf[k] = (text[k] << 8) | color;
295 res = osd_write_videomem(screen, y * BASE_WIDTH + x, buf, len);
303 int osd_probe(unsigned screen)
305 struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
306 struct ihs_osd *osd = &fpga->osd;
307 u16 version = in_le16(&osd->version);
308 u16 features = in_le16(&osd->features);
313 width = ((features & 0x3f00) >> 8) + 1;
314 height = (features & 0x001f) + 1;
316 printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
317 screen, version/100, version%100, width, height);
319 #ifdef CONFIG_SYS_CH7301
320 value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
322 printf(" Probing CH7301 failed, DID %02x\n", value);
325 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
326 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
327 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
328 i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
329 i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
332 #ifdef CONFIG_SYS_MPC92469AC
333 mpc92469ac_set(screen, PIXCLK_640_480_60);
336 #ifdef CONFIG_SYS_ICS8N3QV01
337 ics8n3qv01_set(screen, PIXCLK_640_480_60);
340 #ifdef CONFIG_SYS_SIL1178
341 value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02);
343 printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value);
346 /* magic initialization sequence adapted from datasheet */
347 fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
348 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
349 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
350 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
351 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
352 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
353 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
354 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
355 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
356 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
359 out_le16(&fpga->videocontrol, 0x0002);
360 out_le16(&osd->control, 0x0049);
362 out_le16(&osd->xy_size, ((32 - 1) << 8) | (16 - 1));
363 out_le16(&osd->x_pos, 0x007f);
364 out_le16(&osd->y_pos, 0x005f);
369 int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
373 for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
377 u16 buffer[BASE_WIDTH];
380 unsigned count = (argc > 4) ?
381 simple_strtoul(argv[4], NULL, 16) : 1;
383 if ((argc < 4) || (strlen(argv[3]) % 4)) {
388 x = simple_strtoul(argv[1], NULL, 16);
389 y = simple_strtoul(argv[2], NULL, 16);
396 memcpy(substr, rp, 4);
398 *wp = simple_strtoul(substr, NULL, 16);
402 if (wp - buffer > BASE_WIDTH)
406 for (k = 0; k < count; ++k) {
408 y * BASE_WIDTH + x + k * (wp - buffer);
409 osd_write_videomem(screen, offset, buffer,
418 osdw, 5, 0, osd_write,
419 "write 16-bit hex encoded buffer to osd memory",
420 "pos_x pos_y buffer count\n"
424 osdp, 5, 0, osd_print,
425 "write ASCII buffer to osd memory",
426 "pos_x pos_y color text\n"