3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
14 #include <gdsys_fpga.h>
16 #define ICS8N3QV01_I2C_ADDR 0x6E
17 #define ICS8N3QV01_FREF 114285000
18 #define ICS8N3QV01_FREF_LL 114285000LL
19 #define ICS8N3QV01_F_DEFAULT_0 156250000LL
20 #define ICS8N3QV01_F_DEFAULT_1 125000000LL
21 #define ICS8N3QV01_F_DEFAULT_2 100000000LL
22 #define ICS8N3QV01_F_DEFAULT_3 25175000LL
24 #define SIL1178_MASTER_I2C_ADDRESS 0x38
25 #define SIL1178_SLAVE_I2C_ADDRESS 0x39
27 #define DP501_I2C_ADDR 0x08
29 #define PIXCLK_640_480_60 25180000
30 #define MAX_X_CHARS 53
31 #define MAX_Y_CHARS 26
33 #ifdef CONFIG_SYS_OSD_DH
34 #define MAX_OSD_SCREEN 8
37 #define MAX_OSD_SCREEN 4
40 #ifdef CONFIG_SYS_OSD_DH
41 #define OSD_SET_REG(screen, fld, val) \
43 if (screen >= OSD_DH_BASE) \
44 FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
46 FPGA_SET_REG(screen, osd0.fld, val); \
49 #define OSD_SET_REG(screen, fld, val) \
50 FPGA_SET_REG(screen, osd0.fld, val)
53 #ifdef CONFIG_SYS_OSD_DH
54 #define OSD_GET_REG(screen, fld, val) \
56 if (screen >= OSD_DH_BASE) \
57 FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
59 FPGA_GET_REG(screen, osd0.fld, val); \
62 #define OSD_GET_REG(screen, fld, val) \
63 FPGA_GET_REG(screen, osd0.fld, val)
66 unsigned int base_width;
67 unsigned int base_height;
71 unsigned int osd_screen_mask = 0;
73 #ifdef CONFIG_SYS_ICS8N3QV01_I2C
74 int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
77 #ifdef CONFIG_SYS_SIL1178_I2C
78 int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
81 #ifdef CONFIG_SYS_DP501_I2C
82 int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
85 #ifdef CONFIG_SYS_DP501_BASE
86 int dp501_base[] = CONFIG_SYS_DP501_BASE;
89 #ifdef CONFIG_SYS_MPC92469AC
90 static void mpc92469ac_calc_parameters(unsigned int fout,
91 unsigned int *post_div, unsigned int *feedback_div)
93 unsigned int n = *post_div;
94 unsigned int m = *feedback_div;
96 unsigned int b = 14745600 / 16;
100 else if (fout < 100339199)
102 else if (fout < 200678399)
107 a = fout * n + (b / 2); /* add b/2 for proper rounding */
115 static void mpc92469ac_set(unsigned screen, unsigned int fout)
119 unsigned int bitval = 0;
120 mpc92469ac_calc_parameters(fout, &n, &m);
137 FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m);
141 #ifdef CONFIG_SYS_ICS8N3QV01_I2C
143 static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
145 unsigned long long n;
146 unsigned long long mint;
147 unsigned long long mfrac;
148 u8 reg_a, reg_b, reg_c, reg_d, reg_f;
149 unsigned long long fout_calc;
154 reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index);
155 reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index);
156 reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index);
157 reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index);
158 reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index);
160 mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
161 mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
165 fout_calc = (mint * ICS8N3QV01_FREF_LL
166 + mfrac * ICS8N3QV01_FREF_LL / 262144LL
167 + ICS8N3QV01_FREF_LL / 524288LL
177 static void ics8n3qv01_calc_parameters(unsigned int fout,
178 unsigned int *_mint, unsigned int *_mfrac,
182 unsigned int foutiic;
183 unsigned int fvcoiic;
185 unsigned long long mfrac;
187 n = (2215000000U + fout / 2) / fout;
188 if ((n & 1) && (n > 5))
191 foutiic = fout - (fout / 10000);
192 fvcoiic = foutiic * n;
194 mint = fvcoiic / 114285000;
195 if ((mint < 17) || (mint > 63))
196 printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
198 mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
206 static void ics8n3qv01_set(unsigned int fout)
211 unsigned int fout_calc;
212 unsigned long long fout_prog;
214 u8 reg0, reg4, reg8, reg12, reg18, reg20;
216 fout_calc = ics8n3qv01_get_fout_calc(1);
217 off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
218 / ICS8N3QV01_F_DEFAULT_1;
219 printf(" PLL is off by %lld ppm\n", off_ppm);
220 fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc
221 / ICS8N3QV01_F_DEFAULT_1;
222 ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
224 reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
225 reg0 |= (mint & 0x1f) << 1;
226 reg0 |= (mfrac >> 17) & 0x01;
227 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0);
230 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4);
233 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8);
237 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12);
239 reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03;
241 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18);
243 reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
244 reg20 |= mint & (1 << 5);
245 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20);
249 static int osd_write_videomem(unsigned screen, unsigned offset,
250 u16 *data, size_t charcount)
254 for (k = 0; k < charcount; ++k) {
255 if (offset + k >= bufsize)
257 #ifdef CONFIG_SYS_OSD_DH
258 if (screen >= OSD_DH_BASE)
259 FPGA_SET_REG(screen - OSD_DH_BASE,
260 videomem1[offset + k], data[k]);
262 FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
264 FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
271 static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
280 for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
290 if (!(osd_screen_mask & (1 << screen)))
293 x = simple_strtoul(argv[1], NULL, 16);
294 y = simple_strtoul(argv[2], NULL, 16);
295 color = simple_strtoul(argv[3], NULL, 16);
297 charcount = strlen(text);
298 len = (charcount > bufsize) ? bufsize : charcount;
300 for (k = 0; k < len; ++k)
301 buf[k] = (text[k] << 8) | color;
303 res = osd_write_videomem(screen, y * base_width + x, buf, len);
307 OSD_SET_REG(screen, control, 0x0049);
313 int osd_probe(unsigned screen)
317 int old_bus = i2c_get_bus_num();
318 bool pixclock_present = false;
319 bool output_driver_present = false;
320 #ifdef CONFIG_SYS_DP501_I2C
321 #ifdef CONFIG_SYS_DP501_BASE
322 uint8_t dp501_addr = dp501_base[screen];
324 uint8_t dp501_addr = DP501_I2C_ADDR;
328 OSD_GET_REG(0, version, &version);
329 OSD_GET_REG(0, features, &features);
331 base_width = ((features & 0x3f00) >> 8) + 1;
332 base_height = (features & 0x001f) + 1;
333 bufsize = base_width * base_height;
334 buf = malloc(sizeof(u16) * bufsize);
338 #ifdef CONFIG_SYS_OSD_DH
339 printf("OSD%d-%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
340 (screen >= OSD_DH_BASE) ? (screen - OSD_DH_BASE) : screen,
341 (screen > 3) ? 1 : 0, version/100, version%100, base_width,
344 printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
345 screen, version/100, version%100, base_width, base_height);
349 #ifdef CONFIG_SYS_MPC92469AC
350 pixclock_present = true;
351 mpc92469ac_set(screen, PIXCLK_640_480_60);
354 #ifdef CONFIG_SYS_ICS8N3QV01_I2C
355 i2c_set_bus_num(ics8n3qv01_i2c[screen]);
356 if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
357 ics8n3qv01_set(PIXCLK_640_480_60);
358 pixclock_present = true;
362 if (!pixclock_present)
363 printf(" no pixelclock found\n");
365 /* setup output driver */
367 #ifdef CONFIG_SYS_CH7301_I2C
368 if (!ch7301_probe(screen, true))
369 output_driver_present = true;
372 #ifdef CONFIG_SYS_SIL1178_I2C
373 i2c_set_bus_num(sil1178_i2c[screen]);
374 if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
375 if (i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02) == 0x06) {
377 * magic initialization sequence,
378 * adapted from datasheet
380 i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
381 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
382 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
383 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
384 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
385 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
386 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
387 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
388 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
389 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
390 output_driver_present = true;
395 #ifdef CONFIG_SYS_DP501_I2C
396 i2c_set_bus_num(dp501_i2c[screen]);
397 if (!i2c_probe(dp501_addr)) {
398 dp501_powerup(dp501_addr);
399 output_driver_present = true;
403 if (!output_driver_present)
404 printf(" no output driver found\n");
406 OSD_SET_REG(screen, xy_size, ((32 - 1) << 8) | (16 - 1));
407 OSD_SET_REG(screen, x_pos, 0x007f);
408 OSD_SET_REG(screen, y_pos, 0x005f);
410 if (pixclock_present && output_driver_present)
411 osd_screen_mask |= 1 << screen;
413 i2c_set_bus_num(old_bus);
418 int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
422 if ((argc < 4) || (strlen(argv[3]) % 4)) {
427 for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
431 u16 buffer[base_width];
434 unsigned count = (argc > 4) ?
435 simple_strtoul(argv[4], NULL, 16) : 1;
437 if (!(osd_screen_mask & (1 << screen)))
440 x = simple_strtoul(argv[1], NULL, 16);
441 y = simple_strtoul(argv[2], NULL, 16);
448 memcpy(substr, rp, 4);
450 *wp = simple_strtoul(substr, NULL, 16);
454 if (wp - buffer > base_width)
458 for (k = 0; k < count; ++k) {
460 y * base_width + x + k * (wp - buffer);
461 osd_write_videomem(screen, offset, buffer,
465 OSD_SET_REG(screen, control, 0x0049);
471 int osd_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
482 x = simple_strtoul(argv[1], NULL, 16);
483 y = simple_strtoul(argv[2], NULL, 16);
485 if (!x || (x > 64) || (x > MAX_X_CHARS) ||
486 !y || (y > 32) || (y > MAX_Y_CHARS)) {
491 for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
492 OSD_SET_REG(screen, xy_size, ((x - 1) << 8) | (y - 1));
493 OSD_SET_REG(screen, x_pos, 32767 * (640 - 12 * x) / 65535);
494 OSD_SET_REG(screen, y_pos, 32767 * (480 - 18 * y) / 65535);
501 osdw, 5, 0, osd_write,
502 "write 16-bit hex encoded buffer to osd memory",
503 "pos_x pos_y buffer count\n"
507 osdp, 5, 0, osd_print,
508 "write ASCII buffer to osd memory",
509 "pos_x pos_y color text\n"
513 osdsize, 3, 0, osd_size,
514 "set OSD XY size in characters",
515 "size_x(max. " __stringify(MAX_X_CHARS)
516 ") size_y(max. " __stringify(MAX_Y_CHARS) ")\n"