3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <fdt_support.h>
16 #include <fsl_esdhc.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_mpc83xx_serdes.h>
23 #include <gdsys_fpga.h>
25 #include "../common/osd.h"
26 #include "../common/mclink.h"
27 #include "../common/phy.h"
34 DECLARE_GLOBAL_DATA_PTR;
36 #define MAX_MUX_CHANNELS 2
39 UNITTYPE_MAIN_SERVER = 0,
40 UNITTYPE_MAIN_USER = 1,
41 UNITTYPE_VIDEO_SERVER = 2,
42 UNITTYPE_VIDEO_USER = 3,
47 UNITTYPEPCB_DP_165 = 1,
48 UNITTYPEPCB_DP_300 = 2,
64 COMPRESSION_TYPE1_DELTA = 1,
65 COMPRESSION_TYPE1_TYPE2_DELTA = 3,
86 CARRIER_SPEED_2_5G = 1,
91 MCFPGA_INIT_N = 1 << 1,
92 MCFPGA_PROGRAM_N = 1 << 2,
93 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
94 MCFPGA_RESET_N = 1 << 4,
102 unsigned int mclink_fpgacount;
103 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
105 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
114 res = mclink_send(fpga - 1, regoff, data);
116 printf("mclink_send reg %02lx data %04x returned %d\n",
126 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
132 *data = in_le16(reg);
135 if (fpga > mclink_fpgacount)
137 res = mclink_receive(fpga - 1, regoff, data);
139 printf("mclink_receive reg %02lx returned %d\n",
150 char *s = getenv("serial#");
151 bool hw_type_cat = pca9698_get_value(0x20, 20);
155 printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
167 static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
173 unsigned unit_type_pcb_video;
174 unsigned hardware_version;
175 unsigned feature_compression;
176 unsigned feature_osd;
177 unsigned feature_audio;
178 unsigned feature_sysclock;
179 unsigned feature_ramconfig;
180 unsigned feature_carrier_speed;
181 unsigned feature_carriers;
182 unsigned feature_video_channels;
184 FPGA_GET_REG(fpga, versions, &versions);
185 FPGA_GET_REG(fpga, fpga_version, &fpga_version);
186 FPGA_GET_REG(fpga, fpga_features, &fpga_features);
188 unit_type = (versions & 0xf000) >> 12;
189 unit_type_pcb_video = (versions & 0x01c0) >> 6;
190 feature_compression = (fpga_features & 0xe000) >> 13;
191 feature_osd = fpga_features & (1<<11);
192 feature_audio = (fpga_features & 0x0600) >> 9;
193 feature_sysclock = (fpga_features & 0x0180) >> 7;
194 feature_ramconfig = (fpga_features & 0x0060) >> 5;
195 feature_carrier_speed = fpga_features & (1<<4);
196 feature_carriers = (fpga_features & 0x000c) >> 2;
197 feature_video_channels = fpga_features & 0x0003;
200 case UNITTYPE_MAIN_USER:
201 printf("Mainchannel");
204 case UNITTYPE_VIDEO_USER:
205 printf("Videochannel");
209 printf("UnitType %d(not supported)", unit_type);
213 if (unit_type == UNITTYPE_MAIN_USER) {
215 (!!pca9698_get_value(0x20, 24) << 0)
216 | (!!pca9698_get_value(0x20, 25) << 1)
217 | (!!pca9698_get_value(0x20, 26) << 2)
218 | (!!pca9698_get_value(0x20, 27) << 3)
219 | (!!pca9698_get_value(0x20, 28) << 4);
220 switch (hardware_version) {
222 printf(" HW-Ver 1.00,");
226 printf(" HW-Ver 1.10,");
230 printf(" HW-Ver %d(not supported),",
238 if (unit_type == UNITTYPE_VIDEO_USER) {
239 hardware_version = versions & 0x000f;
240 switch (hardware_version) {
242 printf(" HW-Ver 2.00,");
246 printf(" HW-Ver 2.10,");
250 printf(" HW-Ver %d(not supported),",
256 switch (unit_type_pcb_video) {
257 case UNITTYPEPCB_DVI:
261 case UNITTYPEPCB_DP_165:
262 printf(" DP 165MPix/s,");
265 case UNITTYPEPCB_DP_300:
266 printf(" DP 300MPix/s,");
269 case UNITTYPEPCB_HDMI:
274 printf(" FPGA V %d.%02d\n features:",
275 fpga_version / 100, fpga_version % 100);
278 switch (feature_compression) {
279 case COMPRESSION_NONE:
280 printf(" no compression");
283 case COMPRESSION_TYPE1_DELTA:
284 printf(" type1-deltacompression");
287 case COMPRESSION_TYPE1_TYPE2_DELTA:
288 printf(" type1-deltacompression, type2-inlinecompression");
292 printf(" compression %d(not supported)", feature_compression);
296 printf(", %sosd", feature_osd ? "" : "no ");
298 switch (feature_audio) {
300 printf(", no audio");
304 printf(", audio tx");
308 printf(", audio rx");
312 printf(", audio rx+tx");
316 printf(", audio %d(not supported)", feature_audio);
322 switch (feature_sysclock) {
324 printf("clock 147.456 MHz");
328 printf("clock %d(not supported)", feature_sysclock);
332 switch (feature_ramconfig) {
334 printf(", RAM 32 bit DDR2");
338 printf(", RAM 32 bit DDR3");
342 printf(", RAM %d(not supported)", feature_ramconfig);
346 printf(", %d carrier(s) %s", feature_carriers,
347 feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
349 printf(", %d video channel(s)\n", feature_video_channels);
352 int last_stage_init(void)
357 unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
359 bool hw_type_cat = pca9698_get_value(0x20, 20);
360 bool ch0_rgmii2_present = false;
362 FPGA_GET_REG(0, fpga_features, &fpga_features);
364 /* Turn on Parade DP501 */
365 pca9698_direction_output(0x20, 10, 1);
367 ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
369 /* wait for FPGA done */
370 for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
371 unsigned int ctr = 0;
373 if (i2c_probe(mclink_controllers[k]))
376 while (!(pca953x_get_val(mclink_controllers[k])
380 printf("no done for mclink_controller %d\n", k);
387 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
389 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
390 if ((mux_ch == 1) && !ch0_rgmii2_present)
393 setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
397 /* give slave-PLLs and Parade DP501 some time to be up and running */
400 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
401 slaves = mclink_probe();
402 mclink_fpgacount = 0;
404 print_fpga_info(0, ch0_rgmii2_present);
410 mclink_fpgacount = slaves;
412 for (k = 1; k <= slaves; ++k) {
413 FPGA_GET_REG(k, fpga_features, &fpga_features);
415 print_fpga_info(k, false);
418 miiphy_register(bb_miiphy_buses[k].name,
419 bb_miiphy_read, bb_miiphy_write);
420 setup_88e1514(bb_miiphy_buses[k].name, 0);
428 * provide access to fpga gpios (for I2C bitbang)
429 * (these may look all too simple but make iocon.h much more readable)
431 void fpga_gpio_set(unsigned int bus, int pin)
433 FPGA_SET_REG(bus, gpio.set, pin);
436 void fpga_gpio_clear(unsigned int bus, int pin)
438 FPGA_SET_REG(bus, gpio.clear, pin);
441 int fpga_gpio_get(unsigned int bus, int pin)
445 FPGA_GET_REG(bus, gpio.read, &val);
450 void mpc8308_init(void)
452 pca9698_direction_output(0x20, 4, 1);
455 void mpc8308_set_fpga_reset(unsigned state)
457 pca9698_set_value(0x20, 4, state ? 0 : 1);
460 void mpc8308_setup_hw(void)
462 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
465 * set "startup-finished"-gpios
467 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
468 setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
471 int mpc8308_get_fpga_done(unsigned fpga)
473 return pca9698_get_value(0x20, 19);
476 #ifdef CONFIG_FSL_ESDHC
477 int board_mmc_init(bd_t *bd)
479 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
480 sysconf83xx_t *sysconf = &immr->sysconf;
482 /* Enable cache snooping in eSDHC system configuration register */
483 out_be32(&sysconf->sdhccr, 0x02000000);
485 return fsl_esdhc_mmc_init(bd);
489 static struct pci_region pcie_regions_0[] = {
491 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
492 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
493 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
494 .flags = PCI_REGION_MEM,
497 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
498 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
499 .size = CONFIG_SYS_PCIE1_IO_SIZE,
500 .flags = PCI_REGION_IO,
504 void pci_init_board(void)
506 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
507 sysconf83xx_t *sysconf = &immr->sysconf;
508 law83xx_t *pcie_law = sysconf->pcielaw;
509 struct pci_region *pcie_reg[] = { pcie_regions_0 };
511 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
512 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
514 /* Deassert the resets in the control register */
515 out_be32(&sysconf->pecr1, 0xE0008000);
518 /* Configure PCI Express Local Access Windows */
519 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
520 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
522 mpc83xx_pcie_init(1, pcie_reg);
525 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
527 info->portwidth = FLASH_CFI_16BIT;
528 info->chipwidth = FLASH_CFI_BY16;
529 info->interface = FLASH_CFI_X16;
533 #if defined(CONFIG_OF_BOARD_SETUP)
534 void ft_board_setup(void *blob, bd_t *bd)
536 ft_cpu_setup(blob, bd);
537 fdt_fixup_dr_usb(blob, bd);
538 fdt_fixup_esdhc(blob, bd);
543 * FPGA MII bitbang implementation
556 static int mii_dummy_init(struct bb_miiphy_bus *bus)
561 static int mii_mdio_active(struct bb_miiphy_bus *bus)
563 struct fpga_mii *fpga_mii = bus->priv;
566 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
568 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
573 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
575 struct fpga_mii *fpga_mii = bus->priv;
577 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
582 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
584 struct fpga_mii *fpga_mii = bus->priv;
587 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
589 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
596 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
599 struct fpga_mii *fpga_mii = bus->priv;
601 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
603 *v = ((gpio & GPIO_MDIO) != 0);
608 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
610 struct fpga_mii *fpga_mii = bus->priv;
613 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
615 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
620 static int mii_delay(struct bb_miiphy_bus *bus)
627 struct bb_miiphy_bus bb_miiphy_buses[] = {
630 .init = mii_dummy_init,
631 .mdio_active = mii_mdio_active,
632 .mdio_tristate = mii_mdio_tristate,
633 .set_mdio = mii_set_mdio,
634 .get_mdio = mii_get_mdio,
635 .set_mdc = mii_set_mdc,
637 .priv = &fpga_mii[0],
641 .init = mii_dummy_init,
642 .mdio_active = mii_mdio_active,
643 .mdio_tristate = mii_mdio_tristate,
644 .set_mdio = mii_set_mdio,
645 .get_mdio = mii_get_mdio,
646 .set_mdc = mii_set_mdc,
648 .priv = &fpga_mii[1],
652 .init = mii_dummy_init,
653 .mdio_active = mii_mdio_active,
654 .mdio_tristate = mii_mdio_tristate,
655 .set_mdio = mii_set_mdio,
656 .get_mdio = mii_get_mdio,
657 .set_mdc = mii_set_mdc,
659 .priv = &fpga_mii[2],
663 .init = mii_dummy_init,
664 .mdio_active = mii_mdio_active,
665 .mdio_tristate = mii_mdio_tristate,
666 .set_mdio = mii_set_mdio,
667 .get_mdio = mii_get_mdio,
668 .set_mdc = mii_set_mdc,
670 .priv = &fpga_mii[3],
674 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
675 sizeof(bb_miiphy_buses[0]);