3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <fdt_support.h>
16 #include <fsl_esdhc.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_mpc83xx_serdes.h>
23 #include <gdsys_fpga.h>
25 #include "../common/adv7611.h"
26 #include "../common/ch7301.h"
27 #include "../common/dp501.h"
28 #include "../common/ioep-fpga.h"
29 #include "../common/mclink.h"
30 #include "../common/osd.h"
31 #include "../common/phy.h"
32 #include "../common/fanctrl.h"
39 DECLARE_GLOBAL_DATA_PTR;
41 #define MAX_MUX_CHANNELS 2
45 MCFPGA_INIT_N = 1 << 1,
46 MCFPGA_PROGRAM_N = 1 << 2,
47 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
48 MCFPGA_RESET_N = 1 << 4,
56 unsigned int mclink_fpgacount;
57 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
62 } strider_fans[] = CONFIG_STRIDER_FANS;
64 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
73 res = mclink_send(fpga - 1, regoff, data);
75 printf("mclink_send reg %02lx data %04x returned %d\n",
85 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
94 if (fpga > mclink_fpgacount)
96 res = mclink_receive(fpga - 1, regoff, data);
98 printf("mclink_receive reg %02lx returned %d\n",
109 char *s = getenv("serial#");
110 bool hw_type_cat = pca9698_get_value(0x20, 18);
114 printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
126 int last_stage_init(void)
131 unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
132 #ifdef CONFIG_STRIDER_CPU
133 unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
135 bool hw_type_cat = pca9698_get_value(0x20, 18);
136 bool ch0_sgmii2_present = false;
138 /* Turn on Analog Devices ADV7611 */
139 pca9698_direction_output(0x20, 8, 0);
141 /* Turn on Parade DP501 */
142 pca9698_direction_output(0x20, 10, 1);
144 ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
146 /* wait for FPGA done, then reset FPGA */
147 for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
148 unsigned int ctr = 0;
149 unsigned char *mclink_controllers = mclink_controllers_dvi;
151 #ifdef CONFIG_STRIDER_CPU
152 if (i2c_probe(mclink_controllers[k])) {
153 mclink_controllers = mclink_controllers_dp;
154 if (i2c_probe(mclink_controllers[k]))
158 if (i2c_probe(mclink_controllers[k]))
161 while (!(pca953x_get_val(mclink_controllers[k])
165 printf("no done for mclink_controller %d\n", k);
170 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
171 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
173 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
178 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
180 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
181 if ((mux_ch == 1) && !ch0_sgmii2_present)
184 setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
188 /* give slave-PLLs and Parade DP501 some time to be up and running */
191 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
192 slaves = mclink_probe();
193 mclink_fpgacount = 0;
195 ioep_fpga_print_info(0);
197 if (!adv7611_probe(0))
198 printf(" Advantiv ADV7611 HDMI Receiver\n");
200 #ifdef CONFIG_STRIDER_CON
201 if (ioep_fpga_has_osd(0))
205 #ifdef CONFIG_STRIDER_CPU
206 ch7301_probe(0, false);
207 dp501_probe(0, false);
213 mclink_fpgacount = slaves;
215 #ifdef CONFIG_STRIDER_CPU
216 /* get ADV7611 out of reset, power up DP501, give some time to wakeup */
217 for (k = 1; k <= slaves; ++k)
218 FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
223 for (k = 1; k <= slaves; ++k) {
224 ioep_fpga_print_info(k);
225 #ifdef CONFIG_STRIDER_CON
226 if (ioep_fpga_has_osd(k))
229 #ifdef CONFIG_STRIDER_CPU
230 if (!adv7611_probe(k))
231 printf(" Advantiv ADV7611 HDMI Receiver\n");
232 ch7301_probe(k, false);
233 dp501_probe(k, false);
236 miiphy_register(bb_miiphy_buses[k].name,
237 bb_miiphy_read, bb_miiphy_write);
238 setup_88e1514(bb_miiphy_buses[k].name, 0);
242 for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
243 i2c_set_bus_num(strider_fans[k].bus);
244 init_fan_controller(strider_fans[k].addr);
251 * provide access to fpga gpios (for I2C bitbang)
252 * (these may look all too simple but make iocon.h much more readable)
254 void fpga_gpio_set(unsigned int bus, int pin)
256 FPGA_SET_REG(bus, gpio.set, pin);
259 void fpga_gpio_clear(unsigned int bus, int pin)
261 FPGA_SET_REG(bus, gpio.clear, pin);
264 int fpga_gpio_get(unsigned int bus, int pin)
268 FPGA_GET_REG(bus, gpio.read, &val);
273 void mpc8308_init(void)
275 pca9698_direction_output(0x20, 26, 1);
278 void mpc8308_set_fpga_reset(unsigned state)
280 pca9698_set_value(0x20, 26, state ? 0 : 1);
283 void mpc8308_setup_hw(void)
285 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
288 * set "startup-finished"-gpios
290 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
291 setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
294 int mpc8308_get_fpga_done(unsigned fpga)
296 return pca9698_get_value(0x20, 20);
299 #ifdef CONFIG_FSL_ESDHC
300 int board_mmc_init(bd_t *bd)
302 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
303 sysconf83xx_t *sysconf = &immr->sysconf;
305 /* Enable cache snooping in eSDHC system configuration register */
306 out_be32(&sysconf->sdhccr, 0x02000000);
308 return fsl_esdhc_mmc_init(bd);
312 static struct pci_region pcie_regions_0[] = {
314 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
315 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
316 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
317 .flags = PCI_REGION_MEM,
320 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
321 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
322 .size = CONFIG_SYS_PCIE1_IO_SIZE,
323 .flags = PCI_REGION_IO,
327 void pci_init_board(void)
329 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
330 sysconf83xx_t *sysconf = &immr->sysconf;
331 law83xx_t *pcie_law = sysconf->pcielaw;
332 struct pci_region *pcie_reg[] = { pcie_regions_0 };
334 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
335 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
337 /* Deassert the resets in the control register */
338 out_be32(&sysconf->pecr1, 0xE0008000);
341 /* Configure PCI Express Local Access Windows */
342 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
343 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
345 mpc83xx_pcie_init(1, pcie_reg);
348 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
350 info->portwidth = FLASH_CFI_16BIT;
351 info->chipwidth = FLASH_CFI_BY16;
352 info->interface = FLASH_CFI_X16;
356 #if defined(CONFIG_OF_BOARD_SETUP)
357 int ft_board_setup(void *blob, bd_t *bd)
359 ft_cpu_setup(blob, bd);
360 fdt_fixup_dr_usb(blob, bd);
361 fdt_fixup_esdhc(blob, bd);
368 * FPGA MII bitbang implementation
381 static int mii_dummy_init(struct bb_miiphy_bus *bus)
386 static int mii_mdio_active(struct bb_miiphy_bus *bus)
388 struct fpga_mii *fpga_mii = bus->priv;
391 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
393 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
398 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
400 struct fpga_mii *fpga_mii = bus->priv;
402 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
407 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
409 struct fpga_mii *fpga_mii = bus->priv;
412 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
414 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
421 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
424 struct fpga_mii *fpga_mii = bus->priv;
426 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
428 *v = ((gpio & GPIO_MDIO) != 0);
433 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
435 struct fpga_mii *fpga_mii = bus->priv;
438 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
440 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
445 static int mii_delay(struct bb_miiphy_bus *bus)
452 struct bb_miiphy_bus bb_miiphy_buses[] = {
455 .init = mii_dummy_init,
456 .mdio_active = mii_mdio_active,
457 .mdio_tristate = mii_mdio_tristate,
458 .set_mdio = mii_set_mdio,
459 .get_mdio = mii_get_mdio,
460 .set_mdc = mii_set_mdc,
462 .priv = &fpga_mii[0],
466 .init = mii_dummy_init,
467 .mdio_active = mii_mdio_active,
468 .mdio_tristate = mii_mdio_tristate,
469 .set_mdio = mii_set_mdio,
470 .get_mdio = mii_get_mdio,
471 .set_mdc = mii_set_mdc,
473 .priv = &fpga_mii[1],
477 .init = mii_dummy_init,
478 .mdio_active = mii_mdio_active,
479 .mdio_tristate = mii_mdio_tristate,
480 .set_mdio = mii_set_mdio,
481 .get_mdio = mii_get_mdio,
482 .set_mdc = mii_set_mdc,
484 .priv = &fpga_mii[2],
488 .init = mii_dummy_init,
489 .mdio_active = mii_mdio_active,
490 .mdio_tristate = mii_mdio_tristate,
491 .set_mdio = mii_set_mdio,
492 .get_mdio = mii_get_mdio,
493 .set_mdc = mii_set_mdc,
495 .priv = &fpga_mii[3],
499 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
500 sizeof(bb_miiphy_buses[0]);