1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright (C) 2016 Grinn
7 #include <asm/arch/clock.h>
8 #include <asm/arch/iomux.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/litesom.h>
12 #include <asm/arch/mx6ul_pins.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/boot_mode.h>
20 #include <fsl_esdhc.h>
21 #include <linux/sizes.h>
28 #include <usb/ehci-ci.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
33 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
34 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
37 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
38 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
41 PAD_CTL_SPEED_HIGH | \
42 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
44 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
45 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
47 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
49 static iomux_v3_cfg_t const uart1_pads[] = {
50 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
51 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
54 static iomux_v3_cfg_t const sd_pads[] = {
55 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
56 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
60 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
63 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
67 static iomux_v3_cfg_t const fec1_pads[] = {
68 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
69 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
74 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 static void setup_iomux_fec(void)
82 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
86 static void setup_iomux_uart(void)
88 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
91 #ifdef CONFIG_FSL_ESDHC
92 static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};
94 #define SD_CD_GPIO IMX_GPIO_NR(1, 19)
96 static int mmc_get_env_devno(void)
98 u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
102 bootsel = (soc_sbmr & 0x000000FF) >> 6;
104 /* If not boot from sd/mmc, use default value */
106 return CONFIG_SYS_MMC_ENV_DEV;
108 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
109 dev_no = (soc_sbmr & 0x00001800) >> 11;
114 int board_mmc_getcd(struct mmc *mmc)
116 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
119 switch (cfg->esdhc_base) {
120 case USDHC1_BASE_ADDR:
121 ret = !gpio_get_value(SD_CD_GPIO);
123 case USDHC2_BASE_ADDR:
131 int board_mmc_init(bd_t *bis)
136 imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads));
137 gpio_direction_input(SD_CD_GPIO);
138 sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
140 ret = fsl_esdhc_initialize(bis, &sd_cfg);
142 printf("Warning: failed to initialize mmc dev 0 (SD)\n");
146 return litesom_mmc_init(bis);
149 static int check_mmc_autodetect(void)
151 char *autodetect_str = env_get("mmcautodetect");
153 if ((autodetect_str != NULL) &&
154 (strcmp(autodetect_str, "yes") == 0)) {
161 void board_late_mmc_init(void)
165 u32 dev_no = mmc_get_env_devno();
167 if (!check_mmc_autodetect())
170 env_set_ulong("mmcdev", dev_no);
173 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
175 env_set("mmcroot", mmcblk);
177 sprintf(cmd, "mmc dev %d", dev_no);
182 #ifdef CONFIG_FEC_MXC
183 int board_eth_init(bd_t *bis)
187 return fecmxc_initialize(bis);
190 static int setup_fec(void)
192 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
195 /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13],
197 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
198 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
200 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
210 #ifdef CONFIG_USB_EHCI_MX6
211 int board_usb_phy_mode(int port)
213 return USB_INIT_HOST;
217 int board_early_init_f(void)
226 /* Address of boot parameters */
227 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
229 #ifdef CONFIG_FEC_MXC
236 #ifdef CONFIG_CMD_BMODE
237 static const struct boot_mode board_boot_modes[] = {
238 /* 4 bit bus width */
239 {"sd", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
240 {"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)},
245 int board_late_init(void)
247 #ifdef CONFIG_CMD_BMODE
248 add_board_boot_modes(board_boot_modes);
251 #ifdef CONFIG_ENV_IS_IN_MMC
252 board_late_mmc_init();
260 puts("Board: Grinn liteBoard\n");
265 #ifdef CONFIG_SPL_BUILD
266 void board_boot_order(u32 *spl_boot_list)
268 struct src *psrc = (struct src *)SRC_BASE_ADDR;
269 unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
270 unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
271 unsigned port = (reg >> 11) & 0x1;
274 spl_boot_list[0] = BOOT_DEVICE_MMC1;
275 spl_boot_list[1] = BOOT_DEVICE_MMC2;
277 spl_boot_list[0] = BOOT_DEVICE_MMC2;
278 spl_boot_list[1] = BOOT_DEVICE_MMC1;
282 void board_init_f(ulong dummy)