2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
4 * SPDX-License-Identifier: GPL-2.0
10 #include <asm/addrspace.h>
12 #include <asm/malta.h>
13 #include <pci_gt64120.h>
17 phys_size_t initdram(int board_type)
19 return CONFIG_SYS_MEM_SIZE;
24 puts("Board: MIPS Malta CoreLV (Qemu)\n");
28 int board_eth_init(bd_t *bis)
30 return pci_eth_init(bis);
33 void _machine_restart(void)
35 void __iomem *reset_base;
37 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
38 __raw_writel(GORESET, reset_base);
41 int board_early_init_f(void)
43 /* setup FDC37M817 super I/O controller */
44 malta_superio_init((void *)CKSEG1ADDR(MALTA_IO_PORT_BASE));
49 void pci_init_board(void)
51 set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE));
53 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
54 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
55 0x10000000, 0x10000000, 128 * 1024 * 1024,
56 0x00000000, 0x00000000, 0x20000);