3 * ISEE 2007 SL, <www.iseebcn.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <status_led.h>
16 #include <asm/arch/mem.h>
17 #include <asm/arch/mmc_host_def.h>
18 #include <asm/arch/mux.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-types.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/nand.h>
23 #include <linux/mtd/nand.h>
24 #include <linux/mtd/onenand.h>
25 #include <jffs2/load_kernel.h>
27 #include <fdt_support.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 static const struct ns16550_platdata igep_serial = {
33 .base = OMAP34XX_UART3,
35 .clock = V_NS16550_CLK
38 U_BOOT_DEVICE(igep_uart) = {
45 * Description: Early hardware init.
51 /* find out flash memory type, assume NAND first */
52 gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
55 /* Issue a RESET and then READID */
56 writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
57 writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
58 while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
59 != NAND_STATUS_READY) {
62 gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
63 gpmc_init(); /* reinitialize for OneNAND */
69 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
71 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
72 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
78 #ifdef CONFIG_SPL_BUILD
80 * Routine: get_board_mem_timings
81 * Description: If we use SPL then there is no x-loader nor config header
82 * so we have to setup the DDR timings ourself on both banks.
84 void get_board_mem_timings(struct board_sdrc_timings *timings)
86 int mfr, id, err = identify_nand_chip(&mfr, &id);
88 timings->mr = MICRON_V_MR_165;
92 timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
93 timings->ctrla = HYNIX_V_ACTIMA_200;
94 timings->ctrlb = HYNIX_V_ACTIMB_200;
97 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
98 timings->ctrla = MICRON_V_ACTIMA_200;
99 timings->ctrlb = MICRON_V_ACTIMB_200;
102 /* Should not happen... */
105 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
106 gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
108 if (get_cpu_family() == CPU_OMAP34XX) {
109 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
110 timings->ctrla = NUMONYX_V_ACTIMA_165;
111 timings->ctrlb = NUMONYX_V_ACTIMB_165;
112 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
114 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
115 timings->ctrla = NUMONYX_V_ACTIMA_200;
116 timings->ctrlb = NUMONYX_V_ACTIMB_200;
117 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
119 gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
123 #ifdef CONFIG_SPL_OS_BOOT
124 int spl_start_uboot(void)
126 /* break into full u-boot on 'c' */
127 if (serial_tstc() && serial_getc() == 'c')
135 int onenand_board_init(struct mtd_info *mtd)
137 if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
138 struct onenand_chip *this = mtd->priv;
139 this->base = (void *)CONFIG_SYS_ONENAND_BASE;
145 #if defined(CONFIG_CMD_NET)
146 static void reset_net_chip(int gpio)
148 if (!gpio_request(gpio, "eth nrst")) {
149 gpio_direction_output(gpio, 1);
151 gpio_set_value(gpio, 0);
153 gpio_set_value(gpio, 1);
159 * Routine: setup_net_chip
160 * Description: Setting up the configuration GPMC registers specific to the
163 static void setup_net_chip(void)
165 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
166 static const u32 gpmc_lan_config[] = {
167 NET_LAN9221_GPMC_CONFIG1,
168 NET_LAN9221_GPMC_CONFIG2,
169 NET_LAN9221_GPMC_CONFIG3,
170 NET_LAN9221_GPMC_CONFIG4,
171 NET_LAN9221_GPMC_CONFIG5,
172 NET_LAN9221_GPMC_CONFIG6,
175 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
176 CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
178 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
179 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
180 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
181 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
182 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
183 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
184 &ctrl_base->gpmc_nadv_ale);
189 int board_eth_init(bd_t *bis)
191 #ifdef CONFIG_SMC911X
192 return smc911x_initialize(0, CONFIG_SMC911X_BASE);
198 static inline void setup_net_chip(void) {}
201 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
202 int board_mmc_init(bd_t *bis)
204 return omap_mmc_init(0, 0, 0, -1, -1);
208 #if defined(CONFIG_GENERIC_MMC)
209 void board_mmc_power_init(void)
211 twl4030_power_mmc_init(0);
215 #ifdef CONFIG_OF_BOARD_SETUP
216 int ft_board_setup(void *blob, bd_t *bd)
218 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
219 static struct node_info nodes[] = {
220 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
221 { "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, },
224 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
232 switch (gd->bd->bi_arch_number) {
233 case MACH_TYPE_IGEP0020:
234 setenv("fdtfile", "omap3-igep0020.dtb");
236 case MACH_TYPE_IGEP0030:
237 setenv("fdtfile", "omap3-igep0030.dtb");
243 * Routine: misc_init_r
244 * Description: Configure board specific parts
246 int misc_init_r(void)
248 twl4030_power_init();
252 omap_die_id_display();
259 void board_mtdparts_default(const char **mtdids, const char **mtdparts)
261 struct mtd_info *mtd = get_mtd_device(NULL, 0);
264 static char parts[48];
265 const char *linux_name = "omap2-nand";
266 if (strncmp(mtd->name, "onenand0", 8) == 0)
267 linux_name = "omap2-onenand";
268 snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
269 snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
270 linux_name, 4 * mtd->erasesize >> 10);
277 * Routine: set_muxconf_regs
278 * Description: Setting up the configuration Mux registers specific to the
279 * hardware. Many pins need to be moved from protect to primary
282 void set_muxconf_regs(void)
286 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
290 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)