2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #ifdef CONFIG_STATUS_LED
30 # include <status_led.h>
33 /* ------------------------------------------------------------------------- */
35 static long int dram_size (long int, long int *, long int);
37 /* ------------------------------------------------------------------------- */
39 #define _NOT_USED_ 0xFFFFFFFF
42 * 50 MHz SHARC access using UPM A
44 const uint sharc_table[] =
47 * Single Read. (Offset 0 in UPM RAM)
49 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
50 0xFFFFEC05, /* last */
51 _NOT_USED_, _NOT_USED_, _NOT_USED_,
53 * Burst Read. (Offset 8 in UPM RAM)
56 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
57 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
58 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
59 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
61 * Single Write. (Offset 18 in UPM RAM)
63 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
64 0xFFFFEC05, /* last */
65 _NOT_USED_, _NOT_USED_, _NOT_USED_,
67 * Burst Write. (Offset 20 in UPM RAM)
70 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
71 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
72 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
73 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
75 * Refresh (Offset 30 in UPM RAM)
78 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
79 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
80 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
82 * Exception. (Offset 3c in UPM RAM)
84 0x7FFFFC07, /* last */
85 _NOT_USED_, _NOT_USED_, _NOT_USED_,
90 * 50 MHz SDRAM access using UPM B
92 const uint sdram_table[] =
95 * Single Read. (Offset 0 in UPM RAM)
97 0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45, /* last */
100 * SDRAM Initialization (offset 5 in UPM RAM)
102 * This is no UPM entry point. The following definition uses
103 * the remaining space to establish an initialization
104 * sequence, which is executed by a RUN command.
107 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
109 * Burst Read. (Offset 8 in UPM RAM)
111 0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00,
112 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45, /* last */
114 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
115 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
117 * Single Write. (Offset 18 in UPM RAM)
119 0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */
120 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
122 * Burst Write. (Offset 20 in UPM RAM)
124 0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00,
125 0xE1BBBC04, 0x1FF77C45, /* last */
126 _NOT_USED_, _NOT_USED_,
127 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
128 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
130 * Refresh (Offset 30 in UPM RAM)
132 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84,
133 0xFFFFFC05, /* last */
134 _NOT_USED_, _NOT_USED_, _NOT_USED_,
135 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
137 * Exception. (Offset 3c in UPM RAM)
139 0x7FFFFC07, /* last */
140 _NOT_USED_, _NOT_USED_, _NOT_USED_,
143 /* ------------------------------------------------------------------------- */
147 * Check Board Identity:
151 int checkboard (void)
154 puts ("Board: IVMS8\n");
157 puts ("Board: IVM-L8/24\n");
162 /* ------------------------------------------------------------------------- */
165 initdram (int board_type)
167 volatile immap_t *immr = (immap_t *)CFG_IMMR;
168 volatile memctl8xx_t *memctl = &immr->im_memctl;
171 /* enable SDRAM clock ("switch on" SDRAM) */
172 immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE); /* GPIO */
173 immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE); /* active output */
174 immr->im_cpm.cp_pbdir |= CFG_PB_SDRAM_CLKE ; /* output */
175 immr->im_cpm.cp_pbdat |= CFG_PB_SDRAM_CLKE ; /* assert SDRAM CLKE */
179 * Map controller bank 1 for ELIC SACCO
181 memctl->memc_or1 = CFG_OR1;
182 memctl->memc_br1 = CFG_BR1;
185 * Map controller bank 2 for ELIC EPIC
187 memctl->memc_or2 = CFG_OR2;
188 memctl->memc_br2 = CFG_BR2;
191 * Configure UPMA for SHARC
193 upmconfig(UPMA, (uint *)sharc_table, sizeof(sharc_table)/sizeof(uint));
195 #if defined(CONFIG_IVML24)
197 * Map controller bank 4 for HDLC Address space
199 memctl->memc_or4 = CFG_OR4;
200 memctl->memc_br4 = CFG_BR4;
204 * Map controller bank 5 for SHARC
206 memctl->memc_or5 = CFG_OR5;
207 memctl->memc_br5 = CFG_BR5;
209 memctl->memc_mamr = 0x00001000;
212 * Configure UPMB for SDRAM
214 upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
216 memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
218 memctl->memc_mar = 0x00000088;
221 * Map controller bank 3 to the SDRAM bank at preliminary address.
223 memctl->memc_or3 = CFG_OR3_PRELIM;
224 memctl->memc_br3 = CFG_BR3_PRELIM;
226 memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
229 memctl->memc_mcr = 0x80806105; /* precharge */
231 memctl->memc_mcr = 0x80806106; /* load mode register */
233 memctl->memc_mcr = 0x80806130; /* autorefresh */
235 memctl->memc_mcr = 0x80806130; /* autorefresh */
237 memctl->memc_mcr = 0x80806130; /* autorefresh */
239 memctl->memc_mcr = 0x80806130; /* autorefresh */
241 memctl->memc_mcr = 0x80806130; /* autorefresh */
243 memctl->memc_mcr = 0x80806130; /* autorefresh */
245 memctl->memc_mcr = 0x80806130; /* autorefresh */
247 memctl->memc_mcr = 0x80806130; /* autorefresh */
249 memctl->memc_mbmr |= MAMR_PTBE; /* refresh enabled */
252 * Check Bank 0 Memory Size for re-configuration
254 size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
256 memctl->memc_mbmr = CFG_MBMR_8COL | MAMR_PTBE;
261 /* ------------------------------------------------------------------------- */
264 * Check memory range for valid RAM. A simple memory test determines
265 * the actually available RAM size between addresses `base' and
266 * `base + maxsize'. Some (not all) hardware errors are detected:
267 * - short between address lines
268 * - short between data lines
271 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
273 volatile immap_t *immr = (immap_t *)CFG_IMMR;
274 volatile memctl8xx_t *memctl = &immr->im_memctl;
275 volatile long int *addr;
277 ulong save[32]; /* to make test non-destructive */
280 memctl->memc_mbmr = mamr_value;
282 for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
283 addr = base + cnt; /* pointer arith! */
289 /* write 0 to base address */
294 /* check at base address */
295 if ((val = *addr) != 0) {
300 for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
301 addr = base + cnt; /* pointer arith! */
307 return (cnt * sizeof(long));
313 /* ------------------------------------------------------------------------- */
317 immap_t *immr = (immap_t *)CFG_IMMR;
319 /* De-assert Ethernet Powerdown */
320 immr->im_cpm.cp_pbpar &= ~(CFG_PB_ETH_POWERDOWN); /* GPIO */
321 immr->im_cpm.cp_pbodr &= ~(CFG_PB_ETH_POWERDOWN); /* active output */
322 immr->im_cpm.cp_pbdir |= CFG_PB_ETH_POWERDOWN ; /* output */
323 immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
327 * RESET is implemented by a positive pulse of at least 1 us
330 * Configure RESET pins for NS DP83843 PHY, and RESET chip.
332 * Note: The RESET pin is high active, but there is an
333 * inverter on the SPD823TS board...
335 immr->im_ioport.iop_pcpar &= ~(CFG_PC_ETH_RESET);
336 immr->im_ioport.iop_pcdir |= CFG_PC_ETH_RESET;
337 /* assert RESET signal of PHY */
338 immr->im_ioport.iop_pcdat &= ~(CFG_PC_ETH_RESET);
340 /* de-assert RESET signal of PHY */
341 immr->im_ioport.iop_pcdat |= CFG_PC_ETH_RESET;
345 /* ------------------------------------------------------------------------- */
347 void show_boot_progress (int status)
349 #if defined(CONFIG_STATUS_LED)
350 # if defined(STATUS_LED_YELLOW)
351 status_led_set (STATUS_LED_YELLOW,
352 (status < 0) ? STATUS_LED_ON : STATUS_LED_OFF);
353 # endif /* STATUS_LED_YELLOW */
354 # if defined(STATUS_LED_BOOT)
356 status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
357 # endif /* STATUS_LED_BOOT */
358 #endif /* CONFIG_STATUS_LED */
361 /* ------------------------------------------------------------------------- */
363 void ide_set_reset(int on)
365 volatile immap_t *immr = (immap_t *)CFG_IMMR;
368 * Configure PC for IDE Reset Pin
370 if (on) { /* assert RESET */
371 immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
372 } else { /* release RESET */
373 immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
376 /* program port pin as GPIO output */
377 immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
378 immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
379 immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
382 /* ------------------------------------------------------------------------- */