2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * Based on U-Boot and RedBoot sources for several different i.mx
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/macro.h>
27 write32 0x43f00000, 0x77777777
28 write32 0x43f00004, 0x77777777
29 write32 0x43f00000, 0x77777777
30 write32 0x53f00004, 0x77777777
34 write32 0x43f04000, 0x43210
35 write32 0x43f04100, 0x43210
36 write32 0x43f04200, 0x43210
37 write32 0x43f04300, 0x43210
38 write32 0x43f04400, 0x43210
40 write32 0x43f04010, 0x10
41 write32 0x43f04110, 0x10
42 write32 0x43f04210, 0x10
43 write32 0x43f04310, 0x10
44 write32 0x43f04410, 0x10
46 write32 0x43f04800, 0x0
47 write32 0x43f04900, 0x0
48 write32 0x43f04a00, 0x0
49 write32 0x43f04b00, 0x0
50 write32 0x43f04c00, 0x0
54 write32 0xb8003000, 0x1
61 * first enable CLKO debug output
62 * 0x40000000 enables the debug CLKO signal
63 * 0x05000000 sets CLKO divider to 6
64 * 0x00600000 makes CLKO parent clk the USB clk
66 write32 0x53f80064, 0x45600000
67 write32 0x53f80008, 0x20034000
70 * PCDR2: NFC = 33.25 MHz
71 * This is required for the NAND Flash of this board, which is a Samsung
72 * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
73 * the NFC driver in symmetric (i.e. one-cycle) mode.
75 write32 0x53f80020, 0x01010103
78 * enable all implemented clocks in all three
79 * clock control registers
81 write32 0x53f8000c, 0x1fffffff
82 write32 0x53f80010, 0xffffffff
83 write32 0x53f80014, 0xfdfff
88 * ddr_type is 3.3v SDRAM
90 write32 0x43fac454, 0x800
94 * sdram controller init
96 .macro init_sdram_bank bankaddr, ctl, cfg
100 * reset SDRAM controller
101 * then wait for initialization to complete
105 1: ldr r3, [r0, #0x10]
110 str r1, [r0, #\cfg] /* config */
112 ldr r1, =0x92116480 /* control | precharge */
113 str r1, [r0, #\ctl] /* write command to controller */
114 str r1, [r2, #0x400] /* command encoded in address */
116 ldr r1, =0xa2116480 /* auto refresh */
118 ldrb r3, [r2] /* read dram twice to auto refresh */
121 ldr r1, =0xb2116480 /* control | load mode */
122 str r1, [r0, #\ctl] /* write command to controller */
123 strb r1, [r2, #0x33] /* command encoded in address */
125 ldr r1, =0x82116480 /* control | normal (0)*/
126 str r1, [r0, #\ctl] /* write command to controller */
136 init_sdram_bank 0x80000000, 0x0, 0x4
138 init_sdram_bank 0x90000000, 0x8, 0xc