3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
12 * SPDX-License-Identifier: GPL-2.0+
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/kirkwood.h>
24 #include <asm/arch/mpp.h>
26 #include "../common/common.h"
28 DECLARE_GLOBAL_DATA_PTR;
31 * BOCO FPGA definitions
34 #define REG_CTRL_H 0x02
35 #define MASK_WRL_UNITRUN 0x01
36 #define MASK_RBX_PGY_PRESENT 0x40
37 #define REG_IRQ_CIRQ2 0x2d
38 #define MASK_RBI_DEFECT_16 0x01
40 /* Multi-Purpose Pins Functionality configuration */
41 static const u32 kwmpp_config[] = {
50 #if defined(CONFIG_SYS_I2C_SOFT)
54 #if defined(CONFIG_HARD_I2C)
60 MPP12_GPO, /* Reserved */
63 MPP15_GPIO, /* Not used */
64 MPP16_GPIO, /* Not used */
65 MPP17_GPIO, /* Reserved */
82 MPP34_GPIO, /* CDL1 (input) */
83 MPP35_GPIO, /* CDL2 (input) */
84 MPP36_GPIO, /* MAIN_IRQ (input) */
85 MPP37_GPIO, /* BOARD_LED */
86 MPP38_GPIO, /* Piggy3 LED[1] */
87 MPP39_GPIO, /* Piggy3 LED[2] */
88 MPP40_GPIO, /* Piggy3 LED[3] */
89 MPP41_GPIO, /* Piggy3 LED[4] */
90 MPP42_GPIO, /* Piggy3 LED[5] */
91 MPP43_GPIO, /* Piggy3 LED[6] */
92 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
93 MPP45_GPIO, /* Piggy3 LED[8] */
94 MPP46_GPIO, /* Reserved */
95 MPP47_GPIO, /* Reserved */
96 MPP48_GPIO, /* Reserved */
97 MPP49_GPIO, /* SW_INTOUTn */
101 #if defined(CONFIG_KM_MGCOGE3UN)
103 * Wait for startup OK from mgcoge3ne
105 static int startup_allowed(void)
110 * Read CIRQ16 bit (bit 0)
112 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
113 printf("%s: Error reading Boco\n", __func__);
115 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
121 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
123 * All boards with PIGGY4 connected via a simple switch have ethernet always
126 int ethernet_present(void)
131 int ethernet_present(void)
136 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
137 printf("%s: Error reading Boco\n", __func__);
140 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
147 static int initialize_unit_leds(void)
150 * Init the unit LEDs per default they all are
151 * ok apart from bootstat
155 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
156 printf("%s: Error reading Boco\n", __func__);
159 buf |= MASK_WRL_UNITRUN;
160 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
161 printf("%s: Error writing Boco\n", __func__);
167 static void set_bootcount_addr(void)
170 unsigned int bootcountaddr;
171 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
172 sprintf((char *)buf, "0x%x", bootcountaddr);
173 setenv("bootcountaddr", (char *)buf);
176 int misc_init_r(void)
178 #if defined(CONFIG_KM_MGCOGE3UN)
180 wait_for_ne = getenv("waitforne");
181 if (wait_for_ne != NULL) {
182 if (strcmp(wait_for_ne, "true") == 0) {
186 while (startup_allowed() == 0) {
188 (void) getc(); /* consume input */
195 puts("wait\b\b\b\b");
202 printf("\nAbort waiting for ne\n");
209 initialize_unit_leds();
211 set_bootcount_addr();
215 int board_early_init_f(void)
217 #if defined(CONFIG_SYS_I2C_SOFT)
220 /* set the 2 bitbang i2c pins as output gpios */
221 tmp = readl(KW_GPIO0_BASE + 4);
222 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
224 /* adjust SDRAM size for bank 0 */
225 kw_sdram_size_adjust(0);
226 kirkwood_mpp_conf(kwmpp_config, NULL);
232 /* address of boot parameters */
233 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
236 * The KM_FLASH_GPIO_PIN switches between using a
237 * NAND or a SPI FLASH. Set this pin on start
240 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
241 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
243 #if defined(CONFIG_SYS_I2C_SOFT)
245 * Reinit the GPIO for I2C Bitbang driver so that the now
246 * available gpio framework is consistent. The calls to
247 * direction output in are not necessary, they are already done in
250 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
251 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
254 #if defined(CONFIG_SYS_EEPROM_WREN)
255 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
256 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
259 #if defined(CONFIG_KM_FPGA_CONFIG)
260 trigger_fpga_config();
266 int board_late_init(void)
268 #if defined(CONFIG_KMCOGE5UN)
269 /* I/O pin to erase flash RGPP09 = MPP43 */
270 #define KM_FLASH_ERASE_ENABLE 43
271 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
273 /* if pin 1 do full erase */
274 if (dip_switch != 0) {
275 /* start bootloader */
276 puts("DIP: Enabled\n");
277 setenv("actual_bank", "0");
281 #if defined(CONFIG_KM_FPGA_CONFIG)
282 wait_for_fpga_config();
284 toggle_eeprom_spi_bus();
289 int board_spi_claim_bus(struct spi_slave *slave)
291 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
296 void board_spi_release_bus(struct spi_slave *slave)
298 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
301 #if (defined(CONFIG_KM_PIGGY4_88E6061))
303 #define PHY_LED_SEL_REG 0x18
304 #define PHY_LED0_LINK (0x5)
305 #define PHY_LED1_ACT (0x8<<4)
306 #define PHY_LED2_INT (0xe<<8)
307 #define PHY_SPEC_CTRL_REG 0x1c
308 #define PHY_RGMII_CLK_STABLE (0x1<<10)
309 #define PHY_CLSA (0x1<<1)
311 /* Configure and enable MV88E3018 PHY */
314 char *name = "egiga0";
317 if (miiphy_set_current_dev(name))
320 /* RGMII clk transition on data stable */
321 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
322 printf("Error reading PHY spec ctrl reg\n");
323 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
324 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
325 printf("Error writing PHY spec ctrl reg\n");
328 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
329 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
330 printf("Error writing PHY LED reg\n");
333 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
335 #elif defined(CONFIG_KM_PIGGY4_88E6352)
337 #include <mv88e6352.h>
339 #if defined(CONFIG_KM_NUSA)
340 struct mv88e_sw_reg extsw_conf[] = {
342 * port 0, PIGGY4, autoneg
343 * first the fix for the 1000Mbits Autoneg, this is from
344 * a Marvell errata, the regs are undocumented
346 { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
347 { PHY(0), PHY_STATUS, AN1000FIX },
348 { PHY(0), PHY_PAGE, 0 },
349 /* now the real port and phy configuration */
350 { PORT(0), PORT_PHY, NO_SPEED_FOR },
351 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
352 { PHY(0), PHY_1000_CTRL, NO_ADV },
353 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
354 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
357 { PORT(1), PORT_CTRL, PORT_DIS },
358 { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
359 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
361 { PORT(2), PORT_CTRL, PORT_DIS },
362 { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
363 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
365 { PORT(3), PORT_CTRL, PORT_DIS },
366 { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
367 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
368 /* port 4, ICNEV, SerDes, SGMII */
369 { PORT(4), PORT_STATUS, NO_PHY_DETECT },
370 { PORT(4), PORT_PHY, SPEED_1000_FOR },
371 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
372 { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
373 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
374 /* port 5, CPU_RGMII */
375 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
376 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
377 FULL_DPX_FOR | SPEED_1000_FOR },
378 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
379 /* port 6, unused, this port has no phy */
380 { PORT(6), PORT_CTRL, PORT_DIS },
383 struct mv88e_sw_reg extsw_conf[] = {};
388 #if defined(CONFIG_KM_MVEXTSW_ADDR)
389 char *name = "egiga0";
391 if (miiphy_set_current_dev(name))
394 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
395 ARRAY_SIZE(extsw_conf));
396 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
401 /* Configure and enable MV88E1118 PHY on the piggy*/
404 char *name = "egiga0";
406 if (miiphy_set_current_dev(name))
410 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
415 #if defined(CONFIG_HUSH_INIT_VAR)
416 int hush_init_var(void)
423 #if defined(CONFIG_SYS_I2C_SOFT)
424 void set_sda(int state)
430 void set_scl(int state)
443 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
447 #if defined(CONFIG_POST)
449 #define KM_POST_EN_L 44
450 #define POST_WORD_OFF 8
452 int post_hotkeys_pressed(void)
454 #if defined(CONFIG_KM_COGE5UN)
455 return kw_gpio_get_value(KM_POST_EN_L);
457 return !kw_gpio_get_value(KM_POST_EN_L);
461 ulong post_word_load(void)
463 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
464 return in_le32(addr);
467 void post_word_store(ulong value)
469 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
470 out_le32(addr, value);
473 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
475 *vstart = CONFIG_SYS_SDRAM_BASE;
477 /* we go up to relocation plus a 1 MB margin */
478 *size = CONFIG_SYS_TEXT_BASE - (1<<20);
484 #if defined(CONFIG_SYS_EEPROM_WREN)
485 int eeprom_write_enable(unsigned dev_addr, int state)
487 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
489 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);