3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
38 #include <asm/arch/cpu.h>
39 #include <asm/arch/kirkwood.h>
40 #include <asm/arch/mpp.h>
42 #include "../common/common.h"
44 DECLARE_GLOBAL_DATA_PTR;
47 * BOCO FPGA definitions
50 #define REG_CTRL_H 0x02
51 #define MASK_WRL_UNITRUN 0x01
52 #define MASK_RBX_PGY_PRESENT 0x40
53 #define REG_IRQ_CIRQ2 0x2d
54 #define MASK_RBI_DEFECT_16 0x01
56 /* Multi-Purpose Pins Functionality configuration */
57 u32 kwmpp_config[] = {
66 #if defined(CONFIG_SOFT_I2C)
70 #if defined(CONFIG_HARD_I2C)
76 MPP12_GPO, /* Reserved */
79 MPP15_GPIO, /* Not used */
80 MPP16_GPIO, /* Not used */
81 MPP17_GPIO, /* Reserved */
98 MPP34_GPIO, /* CDL1 (input) */
99 MPP35_GPIO, /* CDL2 (input) */
100 MPP36_GPIO, /* MAIN_IRQ (input) */
101 MPP37_GPIO, /* BOARD_LED */
102 MPP38_GPIO, /* Piggy3 LED[1] */
103 MPP39_GPIO, /* Piggy3 LED[2] */
104 MPP40_GPIO, /* Piggy3 LED[3] */
105 MPP41_GPIO, /* Piggy3 LED[4] */
106 MPP42_GPIO, /* Piggy3 LED[5] */
107 MPP43_GPIO, /* Piggy3 LED[6] */
108 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
109 MPP45_GPIO, /* Piggy3 LED[8] */
110 MPP46_GPIO, /* Reserved */
111 MPP47_GPIO, /* Reserved */
112 MPP48_GPIO, /* Reserved */
113 MPP49_GPIO, /* SW_INTOUTn */
117 #if defined(CONFIG_MGCOGE3UN)
119 * Wait for startup OK from mgcoge3ne
121 int startup_allowed(void)
126 * Read CIRQ16 bit (bit 0)
128 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
129 printf("%s: Error reading Boco\n", __func__);
131 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
137 #if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
138 defined(CONFIG_KM_PIGGY4_88E6352))
140 * All boards with PIGGY4 connected via a simple switch have ethernet always
143 int ethernet_present(void)
148 int ethernet_present(void)
153 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
154 printf("%s: Error reading Boco\n", __func__);
157 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
164 int initialize_unit_leds(void)
167 * Init the unit LEDs per default they all are
168 * ok apart from bootstat
172 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
173 printf("%s: Error reading Boco\n", __func__);
176 buf |= MASK_WRL_UNITRUN;
177 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
178 printf("%s: Error writing Boco\n", __func__);
184 #if defined(CONFIG_BOOTCOUNT_LIMIT)
185 void set_bootcount_addr(void)
188 unsigned int bootcountaddr;
189 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
190 sprintf((char *)buf, "0x%x", bootcountaddr);
191 setenv("bootcountaddr", (char *)buf);
195 int misc_init_r(void)
200 str = getenv("mach_type");
202 mach_type = simple_strtoul(str, NULL, 10);
203 printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
204 gd->bd->bi_arch_number = mach_type;
206 #if defined(CONFIG_MGCOGE3UN)
208 wait_for_ne = getenv("waitforne");
209 if (wait_for_ne != NULL) {
210 if (strcmp(wait_for_ne, "true") == 0) {
214 while (startup_allowed() == 0) {
216 (void) getc(); /* consume input */
223 puts("wait\b\b\b\b");
230 printf("\nAbort waiting for ne\n");
237 initialize_unit_leds();
239 #if defined(CONFIG_BOOTCOUNT_LIMIT)
240 set_bootcount_addr();
245 int board_early_init_f(void)
249 kirkwood_mpp_conf(kwmpp_config, NULL);
252 * The FLASH_GPIO_PIN switches between using a
253 * NAND or a SPI FLASH. Set this pin on start
256 tmp = readl(KW_GPIO0_BASE);
257 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
258 tmp = readl(KW_GPIO0_BASE + 4);
259 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
261 #if defined(CONFIG_SOFT_I2C)
262 /* init the GPIO for I2C Bitbang driver */
263 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
264 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
265 kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0);
266 kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0);
268 #if defined(CONFIG_SYS_EEPROM_WREN)
269 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
270 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
272 #if defined(CONFIG_KM_RECONFIG_XLX)
273 /* trigger the reconfiguration of the xilinx fpga */
274 kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
275 kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
276 kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
283 /* address of boot parameters */
284 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
289 int board_spi_claim_bus(struct spi_slave *slave)
291 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
296 void board_spi_release_bus(struct spi_slave *slave)
298 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
303 /* dram_init must store complete ramsize in gd->ram_size */
305 gd->ram_size = get_ram_size((void *)kw_sdram_bar(0),
310 void dram_init_banksize(void)
314 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
315 gd->bd->bi_dram[i].start = kw_sdram_bar(i);
316 gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
321 #if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
323 #define PHY_LED_SEL 0x18
324 #define PHY_LED0_LINK (0x5)
325 #define PHY_LED1_ACT (0x8<<4)
326 #define PHY_LED2_INT (0xe<<8)
327 #define PHY_SPEC_CTRL 0x1c
328 #define PHY_RGMII_CLK_STABLE (0x1<<10)
329 #define PHY_CLSA (0x1<<1)
331 /* Configure and enable MV88E3018 PHY */
334 char *name = "egiga0";
337 if (miiphy_set_current_dev(name))
340 /* RGMII clk transition on data stable */
341 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0)
342 printf("Error reading PHY spec ctrl reg\n");
343 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL,
344 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0)
345 printf("Error writing PHY spec ctrl reg\n");
348 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL,
349 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0)
350 printf("Error writing PHY LED reg\n");
353 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
356 /* Configure and enable MV88E1118 PHY on the piggy*/
359 char *name = "egiga0";
361 if (miiphy_set_current_dev(name))
365 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
370 #if defined(CONFIG_HUSH_INIT_VAR)
371 int hush_init_var(void)
378 #if defined(CONFIG_BOOTCOUNT_LIMIT)
379 const ulong patterns[] = { 0x00000000,
384 const ulong NBR_OF_PATTERNS = ARRAY_SIZE(patterns);
385 const ulong OFFS_PATTERN = 3;
386 const ulong REPEAT_PATTERN = 1000;
388 void bootcount_store(ulong a)
394 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
395 size += gd->bd->bi_dram[i].size;
396 save_addr = (ulong *)(size - BOOTCOUNT_ADDR);
397 writel(a, save_addr);
398 writel(BOOTCOUNT_MAGIC, &save_addr[1]);
400 for (i = 0; i < REPEAT_PATTERN; i++)
401 writel(patterns[i % NBR_OF_PATTERNS],
402 &save_addr[i+OFFS_PATTERN]);
406 ulong bootcount_load(void)
413 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
414 size += gd->bd->bi_dram[i].size;
415 save_addr = (ulong *)(size - BOOTCOUNT_ADDR);
417 counter = readl(&save_addr[0]);
419 /* Is the counter reliable, check in the big pattern for bit errors */
420 for (i = 0; (i < REPEAT_PATTERN) && (counter != 0); i++) {
421 tmp = readl(&save_addr[i+OFFS_PATTERN]);
422 if (tmp != patterns[i % NBR_OF_PATTERNS])
429 #if defined(CONFIG_SOFT_I2C)
430 void set_sda(int state)
436 void set_scl(int state)
449 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
453 #if defined(CONFIG_POST)
455 #define KM_POST_EN_L 44
456 #define POST_WORD_OFF 8
458 int post_hotkeys_pressed(void)
460 return !kw_gpio_get_value(KM_POST_EN_L);
463 ulong post_word_load(void)
465 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
466 return in_le32(addr);
469 void post_word_store(ulong value)
471 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
472 out_le32(addr, value);
475 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
477 *vstart = CONFIG_SYS_SDRAM_BASE;
479 /* we go up to relocation plus a 1 MB margin */
480 *size = CONFIG_SYS_TEXT_BASE - (1<<20);
486 #if defined(CONFIG_SYS_EEPROM_WREN)
487 int eeprom_write_enable(unsigned dev_addr, int state)
489 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
491 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);