2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include "../common/kup.h"
28 #ifdef CONFIG_KUP4K_LOGO
32 DECLARE_GLOBAL_DATA_PTR;
36 # define debugk(fmt,args...) printf(fmt ,##args)
38 # define debugk(fmt,args...)
42 volatile unsigned char *VmemAddr;
43 volatile unsigned char *RegAddr;
47 /* ------------------------------------------------------------------------- */
49 #ifdef CONFIG_KUP4K_LOGO
50 void lcd_logo(bd_t *bd);
54 /* ------------------------------------------------------------------------- */
56 #define _NOT_USED_ 0xFFFFFFFF
58 const uint sdram_table[] = {
60 * Single Read. (Offset 0 in UPMA RAM)
62 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
63 0x1FF77C47, /* last */
66 * SDRAM Initialization (offset 5 in UPMA RAM)
68 * This is no UPM entry point. The following definition uses
69 * the remaining space to establish an initialization
70 * sequence, which is executed by a RUN command.
73 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
76 * Burst Read. (Offset 8 in UPMA RAM)
78 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
79 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
80 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
81 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
84 * Single Write. (Offset 18 in UPMA RAM)
86 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
87 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
90 * Burst Write. (Offset 20 in UPMA RAM)
92 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
93 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
95 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
96 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
99 * Refresh (Offset 30 in UPMA RAM)
101 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
102 0xFFFFFC84, 0xFFFFFC07, /* last */
103 _NOT_USED_, _NOT_USED_,
104 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
107 * Exception. (Offset 3c in UPMA RAM)
109 0x7FFFFC07, /* last */
110 _NOT_USED_, _NOT_USED_, _NOT_USED_,
113 /* ------------------------------------------------------------------------- */
117 * Check Board Identity:
120 int checkboard (void)
122 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
123 uchar *latch,rev,mod;
126 * Init ChipSelect #4 (CAN + HW-Latch)
128 immap->im_memctl.memc_or4 = 0xFFFF8926;
129 immap->im_memctl.memc_br4 = 0x90000401;
131 latch=(uchar *)0x90000200;
132 rev = (*latch & 0xF8) >> 3;
134 printf ("Board: KUP4K Rev %d.%d\n",rev,mod);
138 /* ------------------------------------------------------------------------- */
140 phys_size_t initdram (int board_type)
142 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
143 volatile memctl8xx_t *memctl = &immap->im_memctl;
144 long int size_b0 = 0;
145 long int size_b1 = 0;
146 long int size_b2 = 0;
148 upmconfig (UPMA, (uint *) sdram_table,
149 sizeof (sdram_table) / sizeof (uint));
152 * Preliminary prescaler for refresh (depends on number of
153 * banks): This value is selected for four cycles every 62.4 us
154 * with two SDRAM banks or four cycles every 31.2 us with one
155 * bank. It will be adjusted after memory sizing.
157 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
159 memctl->memc_mar = 0x00000088;
162 * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
163 * preliminary addresses - these have to be modified after the
164 * SDRAM size has been determined.
166 /* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; */
167 /* memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */
169 /* memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; */
170 /* memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; */
173 memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
177 /* perform SDRAM initializsation sequence */
179 memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
181 memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
183 memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
186 memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
188 memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
190 memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
193 memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
195 memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
197 memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
200 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
204 size_b0 = 0x00800000;
205 size_b1 = 0x00800000;
206 size_b2 = 0x00800000;
207 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
209 memctl->memc_or1 = 0xFF800A00;
210 memctl->memc_br1 = 0x00000081;
211 memctl->memc_or2 = 0xFF000A00;
212 memctl->memc_br2 = 0x00800081;
213 memctl->memc_or3 = 0xFE000A00;
214 memctl->memc_br3 = 0x01000081;
215 #else /* 3 x 16 MB */
216 size_b0 = 0x01000000;
217 size_b1 = 0x01000000;
218 size_b2 = 0x01000000;
219 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
221 memctl->memc_or1 = 0xFF000A00;
222 memctl->memc_br1 = 0x00000081;
223 memctl->memc_or2 = 0xFE000A00;
224 memctl->memc_br2 = 0x01000081;
225 memctl->memc_or3 = 0xFC000A00;
226 memctl->memc_br3 = 0x02000081;
231 return (size_b0 + size_b1 + size_b2);
234 /* ------------------------------------------------------------------------- */
236 int misc_init_r (void)
238 #ifdef CONFIG_STATUS_LED
239 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
241 #ifdef CONFIG_KUP4K_LOGO
245 #endif /* CONFIG_KUP4K_LOGO */
246 #ifdef CONFIG_IDE_LED
247 /* Configure PA8 as output port */
248 immap->im_ioport.iop_padir |= 0x80;
249 immap->im_ioport.iop_paodr |= 0x80;
250 immap->im_ioport.iop_papar &= ~0x80;
251 immap->im_ioport.iop_padat |= 0x80; /* turn it off */
253 load_sernum_ethaddr();
259 #ifdef CONFIG_KUP4K_LOGO
262 void lcd_logo (bd_t * bd)
264 FB_INFO_S1D13xxx fb_info;
267 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
268 volatile memctl8xx_t *memctl;
272 int r = 8, g = 8, b = 4;
275 char tmp[64]; /* long enough for environment variables */
278 immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM);
279 immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM);
280 immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */
281 immr->im_cpm.cp_pbdir |= (PB_LCD_PWM);
283 /*----------------------------------------------------------------------------- */
284 /* Initialize the chip and the frame buffer driver. */
285 /*----------------------------------------------------------------------------- */
286 memctl = &immr->im_memctl;
290 * Init ChipSelect #5 (S1D13768)
292 memctl->memc_or5 = 0xFFC007F0; /* 4 MB 17 WS or externel TA */
293 memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */
296 fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR);
297 fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR);
299 if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28)
300 || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) {
301 printf ("Warning:LCD Controller S1D13706 not found\n");
302 setenv ("lcd", "none");
307 for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) {
308 s1dReg = aS1DRegs_prelimn[i].Index;
309 s1dValue = aS1DRegs_prelimn[i].Value;
310 debugk ("s13768 reg: %02x value: %02x\n",
311 aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value);
312 ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
317 n = getenv_f("lcd", tmp, sizeof (tmp));
319 if (!strcmp ("tft", tmp))
325 if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04)
331 debugk ("Port=0x%02x -> TFT=%d\n", tft,
332 ((S1D_VALUE *) fb_info.RegAddr)[0xAC]);
334 /* init controller */
336 for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) {
337 s1dReg = aS1DRegs_stn[i].Index;
338 s1dValue = aS1DRegs_stn[i].Value;
339 debugk ("s13768 reg: %02x value: %02x\n",
340 aS1DRegs_stn[i].Index,
341 aS1DRegs_stn[i].Value);
342 ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] =
345 n = getenv_f("contrast", tmp, sizeof (tmp));
346 ((S1D_VALUE *) fb_info.RegAddr)[0xB3] =
347 (n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0;
348 switch (bd->bi_busfreq) {
350 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
351 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41;
354 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
355 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
358 printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
360 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
361 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66;
364 /* setenv("lcd","stn"); */
366 for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) {
367 s1dReg = aS1DRegs_tft[i].Index;
368 s1dValue = aS1DRegs_tft[i].Value;
369 debugk ("s13768 reg: %02x value: %02x\n",
370 aS1DRegs_tft[i].Index,
371 aS1DRegs_tft[i].Value);
372 ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
376 switch (bd->bi_busfreq) {
378 printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
380 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42;
381 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30;
384 /* setenv("lcd","tft"); */
387 /* create and set colormap */
391 for (i = 0; i < 256; i++) {
392 r1 = (rs * ((i / (g * b)) % r)) * 255;
393 g1 = (gs * ((i / b) % g)) * 255;
394 b1 = (bs * ((i) % b)) * 255;
395 debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4);
396 S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4),
401 fb = (uchar *) (fb_info.VmemAddr);
402 memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240);
404 #endif /* CONFIG_KUP4K_LOGO */