2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
6 * SPDX-License-Identifier: GPL-2.0+
15 #include "../common/kup.h"
18 static unsigned char swapbyte(unsigned char c);
19 static int read_diag(void);
21 DECLARE_GLOBAL_DATA_PTR;
23 /* ----------------------------------------------------------------------- */
25 #define _NOT_USED_ 0xFFFFFFFF
27 const uint sdram_table[] = {
29 * Single Read. (Offset 0 in UPMA RAM)
31 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
32 0x1FF77C47, /* last */
35 * SDRAM Initialization (offset 5 in UPMA RAM)
37 * This is no UPM entry point. The following definition uses
38 * the remaining space to establish an initialization
39 * sequence, which is executed by a RUN command.
42 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
45 * Burst Read. (Offset 8 in UPMA RAM)
47 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
48 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
49 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
50 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
53 * Single Write. (Offset 18 in UPMA RAM)
55 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
56 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
59 * Burst Write. (Offset 20 in UPMA RAM)
61 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
62 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
64 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
65 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
68 * Refresh (Offset 30 in UPMA RAM)
70 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
71 0xFFFFFC84, 0xFFFFFC07, /* last */
72 _NOT_USED_, _NOT_USED_,
73 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
76 * Exception. (Offset 3c in UPMA RAM)
78 0x7FFFFC07, /* last */
79 _NOT_USED_, _NOT_USED_, _NOT_USED_,
82 /* ----------------------------------------------------------------------- */
85 * Check Board Identity:
90 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
91 uchar rev,mod,tmp,pcf,ak_rev,ak_mod;
94 * Init ChipSelect #4 (CAN + HW-Latch)
96 out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
97 out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
100 * Init ChipSelect #5 (S1D13768)
102 out_be32(&immap->im_memctl.memc_or5, CONFIG_SYS_OR5);
103 out_be32(&immap->im_memctl.memc_br5, CONFIG_SYS_BR5);
105 tmp = swapbyte(in_8((unsigned char*) LATCH_ADDR));
106 rev = (tmp & 0xF8) >> 3;
109 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
112 gd->flags &= ~GD_FLG_SILENT;
114 printf("Board: KUP4K Rev %d.%d AK:",rev,mod);
116 * TI Application report: Before using the IO as an input,
117 * a high must be written to the IO first
120 i2c_write(0x21, 0, 0 , &pcf, 1);
121 if (i2c_read(0x21, 0, 0, &pcf, 1)) {
124 ak_rev = (pcf & 0xF8) >> 3;
125 ak_mod = (pcf & 0x07);
126 printf("%d.%d\n", ak_rev, ak_mod);
131 /* ----------------------------------------------------------------------- */
134 phys_size_t initdram(int board_type)
136 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
137 volatile memctl8xx_t *memctl = &immap->im_memctl;
139 uchar *latch, rev, tmp;
142 * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision
143 * Rev 1..6 -> 48 MB RAM; Rev >= 7 -> 96 MB
145 out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
146 out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
148 latch = (uchar *)0x90000200;
149 tmp = swapbyte(*latch);
150 rev = (tmp & 0xF8) >> 3;
152 upmconfig(UPMA, (uint *) sdram_table,
153 sizeof (sdram_table) / sizeof (uint));
155 out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
157 out_be32(&memctl->memc_mar, 0x00000088);
160 out_be32(&memctl->memc_mamr,
161 CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)));
163 out_be32(&memctl->memc_mamr,
164 CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)));
169 /* perform SDRAM initializsation sequence */
172 out_be32(&memctl->memc_mcr, 0x80002105);
174 out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */
176 out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */
180 out_be32(&memctl->memc_mcr, 0x80004105);
182 out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */
184 out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */
188 out_be32(&memctl->memc_mcr, 0x80006105);
190 out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */
192 out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */
195 setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */
198 out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
201 size = 32 * 3 * 1024 * 1024;
202 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_9COL);
203 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_9COL);
204 out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_9COL);
205 out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_9COL);
206 out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_9COL);
207 out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_9COL);
209 size = 16 * 3 * 1024 * 1024;
210 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_8COL);
211 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_8COL);
212 out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_8COL);
213 out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_8COL);
214 out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_8COL);
215 out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_8COL);
220 /* ----------------------------------------------------------------------- */
223 int misc_init_r(void)
225 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
227 #ifdef CONFIG_IDE_LED
228 /* Configure PA8 as output port */
229 setbits_be16(&immap->im_ioport.iop_padir, PA_8);
230 setbits_be16(&immap->im_ioport.iop_paodr, PA_8);
231 clrbits_be16(&immap->im_ioport.iop_papar, PA_8);
232 setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */
234 load_sernum_ethaddr();
241 static int read_diag(void)
244 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
246 clrbits_be16(&immr->im_ioport.iop_pcdir, PC_4); /* input */
247 clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */
248 setbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* output */
249 clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */
250 setbits_be16(&immr->im_ioport.iop_pcdat, PC_5); /* 1 */
252 if (in_be16(&immr->im_ioport.iop_pcdat) & PC_4) {
253 clrbits_be16(&immr->im_ioport.iop_pcdat, PC_5);/* 0 */
255 if(in_be16(&immr->im_ioport.iop_pcdat) & PC_4)
262 clrbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* input */
266 static unsigned char swapbyte(unsigned char c)
268 unsigned char result = 0;
271 for(i = 0; i < 8; ++i) {
272 result = result << 1;
280 * Device Tree Support
282 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
283 void ft_board_setup(void *blob, bd_t *bd)
285 ft_cpu_setup(blob, bd);
287 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */