git.sur5r.net Git - u-boot/blob - board/liebherr/display5/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 DENX Software Engineering
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <spl.h>
   9 #include <linux/libfdt.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/mx6-ddr.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include "asm/arch/crm_regs.h"
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/arch/imx-regs.h>
  17 #include "asm/arch/iomux.h"
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/gpio.h>
  20 #include <environment.h>
  21 #include <fsl_esdhc.h>
  22 #include <netdev.h>
  23 #include <bootcount.h>
  24 #include "common.h"
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
  29         .dram_sdclk_0 = 0x00000030,
  30         .dram_sdclk_1 = 0x00000030,
  31         .dram_cas = 0x00000030,
  32         .dram_ras = 0x00000030,
  33         .dram_reset = 0x00000030,
  34         .dram_sdcke0 = 0x00003000,
  35         .dram_sdcke1 = 0x00003000,
  36         .dram_sdba2 = 0x00000000,
  37         .dram_sdodt0 = 0x00000030,
  38         .dram_sdodt1 = 0x00000030,
  39
  40         .dram_sdqs0 = 0x00000030,
  41         .dram_sdqs1 = 0x00000030,
  42         .dram_sdqs2 = 0x00000030,
  43         .dram_sdqs3 = 0x00000030,
  44         .dram_sdqs4 = 0x00000030,
  45         .dram_sdqs5 = 0x00000030,
  46         .dram_sdqs6 = 0x00000030,
  47         .dram_sdqs7 = 0x00000030,
  48
  49         .dram_dqm0 = 0x00000030,
  50         .dram_dqm1 = 0x00000030,
  51         .dram_dqm2 = 0x00000030,
  52         .dram_dqm3 = 0x00000030,
  53         .dram_dqm4 = 0x00000030,
  54         .dram_dqm5 = 0x00000030,
  55         .dram_dqm6 = 0x00000030,
  56         .dram_dqm7 = 0x00000030,
  57 };
  58
  59 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
  60         .grp_ddr_type = 0x000c0000,
  61         .grp_ddrmode_ctl = 0x00020000,
  62         .grp_ddrpke = 0x00000000,
  63         .grp_addds = 0x00000030,
  64         .grp_ctlds = 0x00000030,
  65         .grp_ddrmode = 0x00020000,
  66         .grp_b0ds = 0x00000030,
  67         .grp_b1ds = 0x00000030,
  68         .grp_b2ds = 0x00000030,
  69         .grp_b3ds = 0x00000030,
  70         .grp_b4ds = 0x00000030,
  71         .grp_b5ds = 0x00000030,
  72         .grp_b6ds = 0x00000030,
  73         .grp_b7ds = 0x00000030,
  74 };
  75
  76 /* 4x128Mx16.cfg */
  77 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
  78         .p0_mpwldectrl0 = 0x002D0028,
  79         .p0_mpwldectrl1 = 0x0032002D,
  80         .p1_mpwldectrl0 = 0x00210036,
  81         .p1_mpwldectrl1 = 0x0019002E,
  82         .p0_mpdgctrl0 = 0x4349035C,
  83         .p0_mpdgctrl1 = 0x0348033D,
  84         .p1_mpdgctrl0 = 0x43550362,
  85         .p1_mpdgctrl1 = 0x03520316,
  86         .p0_mprddlctl = 0x41393940,
  87         .p1_mprddlctl = 0x3F3A3C47,
  88         .p0_mpwrdlctl = 0x413A423A,
  89         .p1_mpwrdlctl = 0x4042483E,
  90 };
  91
  92 /* MT41K128M16JT-125 (2Gb density) */
  93 static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  94         .mem_speed = 1600,
  95         .density = 2,
  96         .width = 16,
  97         .banks = 8,
  98         .rowaddr = 14,
  99         .coladdr = 10,
 100         .pagesz = 2,
 101         .trcd = 1375,
 102         .trcmin = 4875,
 103         .trasmin = 3500,
 104 };
 105
 106 static void ccgr_init(void)
 107 {
 108         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 109
 110         writel(0x00C03F3F, &ccm->CCGR0);
 111         writel(0x0030FC3F, &ccm->CCGR1);
 112         writel(0x0FFFCFC0, &ccm->CCGR2);
 113         writel(0x3FF00000, &ccm->CCGR3);
 114         writel(0x00FFF300, &ccm->CCGR4);
 115         writel(0x0F0000C3, &ccm->CCGR5);
 116         writel(0x000003FF, &ccm->CCGR6);
 117 }
 118
 119 static void spl_dram_init(void)
 120 {
 121         struct mx6_ddr_sysinfo sysinfo = {
 122                 /* width of data bus:0=16,1=32,2=64 */
 123                 .dsize = 2,
 124                 /* config for full 4GB range so that get_mem_size() works */
 125                 .cs_density = 32, /* 32Gb per CS */
 126                 /* single chip select */
 127                 .ncs = 1,
 128                 .cs1_mirror = 0,
 129                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 130                 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
 131                 .walat = 1,     /* Write additional latency */
 132                 .ralat = 5,     /* Read additional latency */
 133                 .mif3_mode = 3, /* Command prediction working mode */
 134                 .bi_on = 1,     /* Bank interleaving enabled */
 135                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 136                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 137                 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
 138                 .ddr_type = DDR_TYPE_DDR3,
 139                 .refsel = 1,    /* Refresh cycles at 32KHz */
 140                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 141         };
 142
 143         mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 144         mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
 145 }
 146
 147 #ifdef CONFIG_SPL_SPI_SUPPORT
 148 static void displ5_init_ecspi(void)
 149 {
 150         displ5_set_iomux_ecspi_spl();
 151         enable_spi_clk(1, 1);
 152 }
 153 #else
 154 static inline void displ5_init_ecspi(void) { }
 155 #endif
 156
 157 #ifdef CONFIG_SPL_MMC_SUPPORT
 158 static struct fsl_esdhc_cfg usdhc_cfg = {
 159         .esdhc_base = USDHC4_BASE_ADDR,
 160         .max_bus_width = 8,
 161 };
 162
 163 int board_mmc_init(bd_t *bd)
 164 {
 165         displ5_set_iomux_usdhc_spl();
 166
 167         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 168         gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
 169
 170         return fsl_esdhc_initialize(bd, &usdhc_cfg);
 171 }
 172 #endif
 173
 174 void board_init_f(ulong dummy)
 175 {
 176         ccgr_init();
 177
 178         arch_cpu_init();
 179
 180         gpr_init();
 181
 182         /* setup GP timer */
 183         timer_init();
 184
 185         displ5_set_iomux_uart_spl();
 186
 187         /* UART clocks enabled and gd valid - init serial console */
 188         preloader_console_init();
 189
 190         displ5_init_ecspi();
 191
 192         /* DDR initialization */
 193         spl_dram_init();
 194
 195         /* Clear the BSS. */
 196         memset(__bss_start, 0, __bss_end - __bss_start);
 197
 198         displ5_set_iomux_misc_spl();
 199
 200         /* load/boot image from boot device */
 201         board_init_r(NULL, 0);
 202 }
 203
 204 #define EM_PAD IMX_GPIO_NR(3, 29)
 205 int board_check_emergency_pad(void)
 206 {
 207         int ret;
 208
 209         ret = gpio_direction_input(EM_PAD);
 210         if (ret)
 211                 return ret;
 212
 213         return !gpio_get_value(EM_PAD);
 214 }
 215
 216 void board_boot_order(u32 *spl_boot_list)
 217 {
 218         /* Default boot sequence SPI -> MMC */
 219         spl_boot_list[0] = spl_boot_device();
 220         spl_boot_list[1] = BOOT_DEVICE_MMC1;
 221         spl_boot_list[2] = BOOT_DEVICE_UART;
 222         spl_boot_list[3] = BOOT_DEVICE_NONE;
 223
 224         /*
 225          * In case of emergency PAD pressed, we always boot
 226          * to proper u-boot and perform recovery tasks there.
 227          */
 228         if (board_check_emergency_pad())
 229                 return;
 230
 231 #ifdef CONFIG_SPL_ENV_SUPPORT
 232         /* 'fastboot' */
 233         const char *s;
 234
 235         if (env_init() || env_load())
 236                 return;
 237
 238         s = env_get("BOOT_FROM");
 239         if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
 240                 spl_boot_list[0] = BOOT_DEVICE_MMC1;
 241                 spl_boot_list[1] = spl_boot_device();
 242         }
 243 #endif
 244 }
 245
 246 void reset_cpu(ulong addr) {}
 247
 248 #ifdef CONFIG_SPL_LOAD_FIT
 249 int board_fit_config_name_match(const char *name)
 250 {
 251         return 0;
 252 }
 253 #endif
 254
 255 #ifdef CONFIG_SPL_OS_BOOT
 256 /* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
 257 int spl_start_uboot(void)
 258 {
 259         /* break into full u-boot on 'c' */
 260         if (serial_tstc() && serial_getc() == 'c')
 261                 return 1;
 262
 263 #ifdef CONFIG_SPL_ENV_SUPPORT
 264         if (env_get_yesno("boot_os") != 1)
 265                 return 1;
 266 #endif
 267         return 0;
 268 }
 269 #endif