git.sur5r.net Git - u-boot/blob - board/liebherr/mccmon6/mccmon6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016-2017
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/iomux.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/mx6-pins.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/gpio.h>
  14 #include <asm/mach-imx/iomux-v3.h>
  15 #include <asm/mach-imx/mxc_i2c.h>
  16 #include <asm/mach-imx/spi.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/io.h>
  19 #include <fsl_esdhc.h>
  20 #include <mmc.h>
  21 #include <netdev.h>
  22 #include <micrel.h>
  23 #include <phy.h>
  24 #include <input.h>
  25 #include <i2c.h>
  26 #include <spl.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  31         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  32         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  33
  34 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  35         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  36         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  37
  38 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  39         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  40
  41 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  42         PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  43
  44 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  46         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  47
  48 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
  49         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  50         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  51
  52 #define USDHC2_CD_GPIO          IMX_GPIO_NR(1, 4)
  53 #define ETH_PHY_RESET           IMX_GPIO_NR(1, 27)
  54 #define ECSPI3_CS0              IMX_GPIO_NR(4, 24)
  55 #define ECSPI3_FLWP             IMX_GPIO_NR(4, 27)
  56 #define NOR_WP                  IMX_GPIO_NR(1, 1)
  57 #define DISPLAY_EN              IMX_GPIO_NR(1, 2)
  58
  59 int dram_init(void)
  60 {
  61         gd->ram_size = imx_ddr_size();
  62
  63         return 0;
  64 }
  65
  66 static iomux_v3_cfg_t const uart1_pads[] = {
  67         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  68         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  69 };
  70
  71 static iomux_v3_cfg_t const usdhc2_pads[] = {
  72         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  73         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  74         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  75         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  76         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  77         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  78         /* Carrier MicroSD Card Detect */
  79         IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  80 };
  81
  82 static iomux_v3_cfg_t const usdhc3_pads[] = {
  83         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  84         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  85         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  86         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  87         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  88         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  89         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  90         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  91         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  92         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  93         IOMUX_PADS(PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  94 };
  95
  96 static iomux_v3_cfg_t const enet_pads[] = {
  97         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  98         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  99         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 100         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 101         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 102         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 103         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 104         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
 105                    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 106         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
 107                    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 108         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 109         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 110         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 111         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 112         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 113         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
 114                    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 115         /* KSZ9031 PHY Reset */
 116         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 117 };
 118
 119 static void setup_iomux_uart(void)
 120 {
 121         SETUP_IOMUX_PADS(uart1_pads);
 122 }
 123
 124 static void setup_iomux_enet(void)
 125 {
 126         SETUP_IOMUX_PADS(enet_pads);
 127
 128         /* Reset KSZ9031 PHY */
 129         gpio_direction_output(ETH_PHY_RESET, 0);
 130         mdelay(10);
 131         gpio_set_value(ETH_PHY_RESET, 1);
 132         udelay(100);
 133 }
 134
 135 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 136         {USDHC3_BASE_ADDR},
 137         {USDHC2_BASE_ADDR},
 138 };
 139
 140 int board_mmc_getcd(struct mmc *mmc)
 141 {
 142         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 143         int ret = 0;
 144
 145         switch (cfg->esdhc_base) {
 146         case USDHC2_BASE_ADDR:
 147                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 148                 break;
 149         case USDHC3_BASE_ADDR:
 150                 /*
 151                  * eMMC don't have card detect pin - since it is soldered to the
 152                  * PCB board
 153                  */
 154                 ret = 1;
 155                 break;
 156         }
 157         return ret;
 158 }
 159
 160 int board_mmc_init(bd_t *bis)
 161 {
 162         int ret;
 163         u32 index = 0;
 164
 165         /*
 166          * MMC MAP
 167          * (U-Boot device node)    (Physical Port)
 168          * mmc0                    Soldered on board eMMC device
 169          * mmc1                    MicroSD card
 170          */
 171         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 172                 switch (index) {
 173                 case 0:
 174                         SETUP_IOMUX_PADS(usdhc3_pads);
 175                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 176                         usdhc_cfg[0].max_bus_width = 8;
 177                         break;
 178                 case 1:
 179                         SETUP_IOMUX_PADS(usdhc2_pads);
 180                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 181                         usdhc_cfg[1].max_bus_width = 4;
 182                         gpio_direction_input(USDHC2_CD_GPIO);
 183                         break;
 184                 default:
 185                         printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
 186                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 187                         return -EINVAL;
 188                 }
 189
 190                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 191                 if (ret)
 192                         return ret;
 193         }
 194
 195         return 0;
 196 }
 197
 198 static iomux_v3_cfg_t const eimnor_pads[] = {
 199         IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 200         IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 201         IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 202         IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 203         IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 204         IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 205         IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 206         IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 207         IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 208         IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 209         IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 210         IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 211         IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 212         IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 213         IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 214         IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 215         IOMUX_PADS(PAD_EIM_DA0__EIM_AD00   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 216         IOMUX_PADS(PAD_EIM_DA1__EIM_AD01   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 217         IOMUX_PADS(PAD_EIM_DA2__EIM_AD02   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 218         IOMUX_PADS(PAD_EIM_DA3__EIM_AD03   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 219         IOMUX_PADS(PAD_EIM_DA4__EIM_AD04   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 220         IOMUX_PADS(PAD_EIM_DA5__EIM_AD05   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 221         IOMUX_PADS(PAD_EIM_DA6__EIM_AD06   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 222         IOMUX_PADS(PAD_EIM_DA7__EIM_AD07   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 223         IOMUX_PADS(PAD_EIM_DA8__EIM_AD08   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 224         IOMUX_PADS(PAD_EIM_DA9__EIM_AD09   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 225         IOMUX_PADS(PAD_EIM_DA10__EIM_AD10  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 226         IOMUX_PADS(PAD_EIM_DA11__EIM_AD11  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 227         IOMUX_PADS(PAD_EIM_DA12__EIM_AD12  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 228         IOMUX_PADS(PAD_EIM_DA13__EIM_AD13  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 229         IOMUX_PADS(PAD_EIM_DA14__EIM_AD14  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 230         IOMUX_PADS(PAD_EIM_DA15__EIM_AD15  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 231         IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 232         IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 233         IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 234         IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 235         IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 236         IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 237         IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 238         IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 239         IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 240         IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 241         IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 242         IOMUX_PADS(PAD_EIM_RW__EIM_RW           | MUX_PAD_CTRL(NO_PAD_CTRL)),
 243         IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 244         IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 245 };
 246
 247 static void eimnor_cs_setup(void)
 248 {
 249         struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
 250
 251
 252         /* NOR configuration */
 253         writel(0x00620181, &weim_regs->cs0gcr1);
 254         writel(0x00000001, &weim_regs->cs0gcr2);
 255         writel(0x0b020000, &weim_regs->cs0rcr1);
 256         writel(0x0000b000, &weim_regs->cs0rcr2);
 257         writel(0x0804a240, &weim_regs->cs0wcr1);
 258         writel(0x00000000, &weim_regs->cs0wcr2);
 259
 260         writel(0x00000120, &weim_regs->wcr);
 261         writel(0x00000010, &weim_regs->wiar);
 262         writel(0x00000000, &weim_regs->ear);
 263
 264         set_chipselect_size(CS0_128);
 265 }
 266
 267 static void setup_eimnor(void)
 268 {
 269         SETUP_IOMUX_PADS(eimnor_pads);
 270         gpio_direction_output(NOR_WP, 1);
 271
 272         enable_eim_clk(1);
 273         eimnor_cs_setup();
 274 }
 275
 276 /* mccmon6 board has SPI Flash is connected to SPI3 */
 277 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 278 {
 279         return (bus == 2 && cs == 0) ? ECSPI3_CS0 : -1;
 280 }
 281
 282 static iomux_v3_cfg_t const ecspi3_pads[] = {
 283         /* SPI3 */
 284         IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 285         IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 286         IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 287         IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 288 };
 289
 290 void setup_spi(void)
 291 {
 292         SETUP_IOMUX_PADS(ecspi3_pads);
 293
 294         enable_spi_clk(true, 2);
 295
 296         /* set cs0 to high */
 297         gpio_direction_output(ECSPI3_CS0, 1);
 298
 299         /* set flwp to high */
 300         gpio_direction_output(ECSPI3_FLWP, 1);
 301 }
 302
 303 struct i2c_pads_info mx6q_i2c1_pad_info = {
 304         .scl = {
 305                 .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL
 306                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 307                 .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27
 308                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 309                 .gp = IMX_GPIO_NR(5, 27)
 310         },
 311         .sda = {
 312                 .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA
 313                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 314                 .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26
 315                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 316                 .gp = IMX_GPIO_NR(5, 26)
 317         }
 318 };
 319
 320 struct i2c_pads_info mx6q_i2c2_pad_info = {
 321         .scl = {
 322                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
 323                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 324                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
 325                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 326                 .gp = IMX_GPIO_NR(4, 12)
 327         },
 328         .sda = {
 329                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
 330                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 331                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
 332                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 333                 .gp = IMX_GPIO_NR(4, 13)
 334         }
 335 };
 336
 337 int board_eth_init(bd_t *bis)
 338 {
 339         setup_iomux_enet();
 340
 341         return cpu_eth_init(bis);
 342 }
 343
 344 int board_early_init_f(void)
 345 {
 346         setup_iomux_uart();
 347
 348         return 0;
 349 }
 350
 351 int board_init(void)
 352 {
 353         /* address of boot parameters */
 354         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 355
 356         gpio_direction_output(DISPLAY_EN, 1);
 357
 358         setup_eimnor();
 359         setup_spi();
 360
 361         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c1_pad_info);
 362         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
 363
 364         return 0;
 365 }
 366
 367 int board_late_init(void)
 368 {
 369         env_set("board_name", "mccmon6");
 370
 371         return 0;
 372 }
 373
 374 int checkboard(void)
 375 {
 376         puts("Board: MCCMON6\n");
 377
 378         return 0;
 379 }
 380
 381 int board_phy_config(struct phy_device *phydev)
 382 {
 383         /*
 384          * Default setting for GMII Clock Pad Skew Register 0x1EF:
 385          * MMD Address 0x2h, Register 0x8h
 386          *
 387          * GTX_CLK Pad Skew 0xF -> 0.9 nsec skew
 388          * RX_CLK Pad Skew 0xF -> 0.9 nsec skew
 389          *
 390          * Adjustment -> write 0x3FF:
 391          * GTX_CLK Pad Skew 0x1F -> 1.8 nsec skew
 392          * RX_CLK Pad Skew 0x1F -> 1.8 nsec skew
 393          *
 394          */
 395         ksz9031_phy_extended_write(phydev, 0x2,
 396                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 397                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x3FF);
 398
 399         ksz9031_phy_extended_write(phydev, 0x02,
 400                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 401                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x00FF);
 402
 403         ksz9031_phy_extended_write(phydev, 0x2,
 404                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 405                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
 406                                    0x3333);
 407
 408         ksz9031_phy_extended_write(phydev, 0x2,
 409                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 410                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
 411                                    0x2052);
 412
 413         if (phydev->drv->config)
 414                 phydev->drv->config(phydev);
 415
 416         return 0;
 417 }
 418
 419 #ifdef CONFIG_SPL_BOARD_INIT
 420 void spl_board_init(void)
 421 {
 422         setup_eimnor();
 423
 424         gpio_direction_output(DISPLAY_EN, 1);
 425 }
 426 #endif /* CONFIG_SPL_BOARD_INIT */
 427
 428 #ifdef CONFIG_SPL_BUILD
 429 void board_boot_order(u32 *spl_boot_list)
 430 {
 431         switch (spl_boot_device()) {
 432         case BOOT_DEVICE_MMC2:
 433         case BOOT_DEVICE_MMC1:
 434                 spl_boot_list[0] = BOOT_DEVICE_MMC2;
 435                 spl_boot_list[1] = BOOT_DEVICE_MMC1;
 436                 break;
 437
 438         case BOOT_DEVICE_NOR:
 439                 spl_boot_list[0] = BOOT_DEVICE_NOR;
 440                 break;
 441         }
 442 }
 443 #endif /* CONFIG_SPL_BUILD */
 444
 445 #ifdef CONFIG_SPL_OS_BOOT
 446 int spl_start_uboot(void)
 447 {
 448         char s[16];
 449         int ret;
 450         /*
 451          * We use BOOT_DEVICE_MMC1, but SD card is connected
 452          * to MMC2
 453          *
 454          * Correct "mapping" is delivered in board defined
 455          * board_boot_order() function.
 456          *
 457          * SD card boot is regarded as a "development" one,
 458          * hence we _always_ go through the u-boot.
 459          *
 460          */
 461         if (spl_boot_device() == BOOT_DEVICE_MMC1)
 462                 return 1;
 463
 464         /* break into full u-boot on 'c' */
 465         if (serial_tstc() && serial_getc() == 'c')
 466                 return 1;
 467
 468         env_init();
 469         ret = env_get_f("boot_os", s, sizeof(s));
 470         if ((ret != -1) && (strcmp(s, "no") == 0))
 471                 return 1;
 472
 473         /*
 474          * Check if SWUpdate recovery needs to be started
 475          *
 476          * recovery_status = NULL (not set - ret == -1) -> normal operation
 477          *
 478          * recovery_status = progress or
 479          * recovery_status = failed   or
 480          * recovery_status = <any value> -> start SWUpdate
 481          *
 482          */
 483         ret = env_get_f("recovery_status", s, sizeof(s));
 484         if (ret != -1)
 485                 return 1;
 486
 487         return 0;
 488 }
 489 #endif /* CONFIG_SPL_OS_BOOT */