3 * Logic Product Development <www.logicpd.com>
6 * Peter Barada <peter.barada@logicpd.com>
8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/mux.h>
25 #include <asm/arch/mem.h>
26 #include <asm/arch/sys_proto.h>
28 #include <asm/mach-types.h>
29 #include <linux/mtd/nand.h>
30 #include "omap3logic.h"
32 DECLARE_GLOBAL_DATA_PTR;
34 #define CONTROL_WKUP_CTRL 0x48002a5c
35 #define GPIO_IO_PWRDNZ (1 << 6)
36 #define PBIASLITEVMODE1 (1 << 8)
39 * two dimensional array of strucures containining board name and Linux
40 * machine IDs; row it selected based on CPU column is slected based
41 * on hsusb0_data5 pin having a pulldown resistor
44 static const struct ns16550_platdata omap3logic_serial = {
50 U_BOOT_DEVICE(omap3logic_uart) = {
55 static struct board_id {
61 .name = "OMAP35xx SOM LV",
62 .machine_id = MACH_TYPE_OMAP3530_LV_SOM,
65 .name = "OMAP35xx Torpedo",
66 .machine_id = MACH_TYPE_OMAP3_TORPEDO,
71 .name = "DM37xx SOM LV",
72 .machine_id = MACH_TYPE_DM3730_SOM_LV,
75 .name = "DM37xx Torpedo",
76 .machine_id = MACH_TYPE_DM3730_TORPEDO,
81 #ifdef CONFIG_SPL_OS_BOOT
82 int spl_start_uboot(void)
84 /* break into full u-boot on 'c' */
85 return serial_tstc() && serial_getc() == 'c';
89 #if defined(CONFIG_SPL_BUILD)
91 * Routine: get_board_mem_timings
92 * Description: If we use SPL then there is no x-loader nor config header
93 * so we have to setup the DDR timings ourself on the first bank. This
94 * provides the timing values back to the function that configures
97 void get_board_mem_timings(struct board_sdrc_timings *timings)
99 timings->mr = MICRON_V_MR_165;
101 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
102 timings->ctrla = MICRON_V_ACTIMA_200;
103 timings->ctrlb = MICRON_V_ACTIMB_200;
104 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
109 * Routine: misc_init_r
110 * Description: Configure board specific parts
112 int misc_init_r(void)
114 t2_t *t2_base = (t2_t *)T2_BASE;
116 /* set up dual-voltage GPIOs to 1.8V */
117 pbias_lite = readl(&t2_base->pbias_lite);
118 pbias_lite &= ~PBIASLITEVMODE1;
119 pbias_lite |= PBIASLITEPWRDNZ1;
120 writel(pbias_lite, &t2_base->pbias_lite);
121 if (get_cpu_family() == CPU_OMAP36XX)
122 writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ,
124 twl4030_power_init();
126 omap_die_id_display();
133 * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
135 #define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
138 * Routine: board_init
139 * Description: Early hardware init.
143 struct board_id *board;
146 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
148 /* boot param addr */
149 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
152 * To identify between a SOM LV and Torpedo module,
153 * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
154 * Drive the pin (and let it soak), then read it back.
155 * If the pin is still high its a Torpedo. If low its a SOM LV
158 /* Mux hsusb0_data5 as a GPIO */
159 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4));
161 if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
164 * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
165 * will drain the voltage.
167 gpio_direction_output(BOARD_ID_GPIO, 0);
168 gpio_set_value(BOARD_ID_GPIO, 1);
170 /* Let it soak for a bit */
174 * Read state of BOARD_ID_GPIO as an input and if its set.
175 * If so the board is a Torpedo
177 gpio_direction_input(BOARD_ID_GPIO);
178 val = gpio_get_value(BOARD_ID_GPIO);
179 gpio_free(BOARD_ID_GPIO);
181 board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
182 printf("Board: %s\n", board->name);
184 /* Set the machine_id passed to Linux */
185 gd->bd->bi_arch_number = board->machine_id;
188 /* restore hsusb0_data5 pin as hsusb0_data5 */
189 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
194 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
195 int board_mmc_init(bd_t *bis)
197 return omap_mmc_init(0, 0, 0, -1, -1);
201 #if defined(CONFIG_GENERIC_MMC)
202 void board_mmc_power_init(void)
204 twl4030_power_mmc_init(0);
208 #ifdef CONFIG_SMC911X
209 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
210 static const u32 gpmc_lan92xx_config[] = {
211 NET_LAN92XX_GPMC_CONFIG1,
212 NET_LAN92XX_GPMC_CONFIG2,
213 NET_LAN92XX_GPMC_CONFIG3,
214 NET_LAN92XX_GPMC_CONFIG4,
215 NET_LAN92XX_GPMC_CONFIG5,
216 NET_LAN92XX_GPMC_CONFIG6,
219 int board_eth_init(bd_t *bis)
221 enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
222 CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
224 return smc911x_initialize(0, CONFIG_SMC911X_BASE);
230 * IDIS - Input Disable
231 * PTD - Pull type Down
233 * DIS - Pull type selection is inactive
234 * EN - Pull type selection is active
236 * The commented string gives the final mux configuration for that pin
240 * Routine: set_muxconf_regs
241 * Description: Setting up the configuration Mux registers specific to the
242 * hardware. Many pins need to be moved from protect to primary
245 void set_muxconf_regs(void)
247 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
248 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
249 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
250 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
251 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
252 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
253 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
254 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
255 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
256 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
257 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
258 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
259 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
260 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
261 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
262 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
263 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
264 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
265 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
266 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
267 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
268 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
269 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
270 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
271 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
272 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
273 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
274 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
275 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
276 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
277 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
278 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
279 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
280 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
281 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
282 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
283 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
284 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
285 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
287 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
288 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
289 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
290 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
291 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
292 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
293 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
294 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
295 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
296 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
297 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
298 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
299 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
300 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
301 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
302 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
303 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
304 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
305 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
306 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
307 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
308 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
309 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
310 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
311 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
312 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
313 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
314 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /*GPMC_nCS1*/
315 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /*GPMC_nCS2*/
316 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /*GPMC_nCS3*/
317 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
318 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); /*GPMC_nCS5*/
319 MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)); /*GPMC_nCS6*/
320 MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)); /*GPMC_nCS7*/
321 MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); /*GPMC_CLK*/
322 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/
323 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/
324 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/
325 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*GPMC_nBE0_CLE*/
326 MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); /*GPMC_nBE1*/
327 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*GPMC_nWP*/
328 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*GPMC_WAIT0*/
329 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /*GPMC_WAIT1*/
330 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/
331 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/
333 MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)); /*CAM_HS */
334 MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)); /*CAM_VS */
335 MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)); /*CAM_XCLKA*/
336 MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)); /*CAM_PCLK*/
337 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)); /*GPIO_98*/
338 MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)); /*CAM_D0*/
339 MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)); /*CAM_D1*/
340 MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)); /*CAM_D2*/
341 MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)); /*CAM_D3*/
342 MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)); /*CAM_D4*/
343 MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)); /*CAM_D5*/
344 MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)); /*CAM_D6*/
345 MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)); /*CAM_D7*/
346 MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)); /*CAM_D8*/
347 MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)); /*CAM_D9*/
348 MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)); /*CAM_D10*/
349 MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)); /*CAM_D11*/
350 MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)); /*CAM_XCLKB*/
351 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)); /*GPIO_167*/
352 MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)); /*CAM_STROBE*/
354 MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)); /*CSI2_DX0*/
355 MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)); /*CSI2_DY0*/
356 MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)); /*CSI2_DX1*/
357 MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)); /*CSI2_DY1*/
359 MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)); /*McBSP2_FSX*/
360 MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)); /*McBSP2_CLKX*/
361 MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)); /*McBSP2_DR*/
362 MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)); /*McBSP2_DX*/
364 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
365 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
366 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
367 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
368 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
369 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
370 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/
371 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/
372 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/
373 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/
375 MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)); /*MMC2_CLK*/
376 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)); /*MMC2_CMD*/
377 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)); /*MMC2_DAT0*/
378 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)); /*MMC2_DAT1*/
379 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)); /*MMC2_DAT2*/
380 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)); /*MMC2_DAT3*/
381 MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M0)); /*MMC2_DAT4*/
382 MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M0)); /*MMC2_DAT5*/
383 MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M0)); /*MMC2_DAT6 */
384 MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)); /*MMC2_DAT7*/
386 MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)); /*McBSP3_DX*/
387 MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)); /*McBSP3_DR*/
388 MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)); /*McBSP3_CLKX*/
389 MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)); /*McBSP3_FSX*/
391 MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)); /*UART2_CTS*/
392 MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)); /*UART2_RTS*/
393 MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)); /*UART2_TX*/
394 MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)); /*UART2_RX*/
396 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/
397 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/
398 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/
399 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/
401 MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/
402 MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)); /*GPIO_153*/
404 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)); /*MCBSP1_CLKR*/
405 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)); /*MCBSP1_FSR*/
406 MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)); /*MCBSP1_DX*/
407 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)); /*MCBSP1_DR*/
408 MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)); /*MCBSP_CLKS*/
409 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)); /*MCBSP1_FSX*/
410 MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)); /*MCBSP1_CLKX*/
412 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); /*UART3_CTS_*/
413 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); /*UART3_RTS_SD */
414 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX_IRRX*/
415 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX_IRTX*/
417 MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
418 MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
419 MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
420 MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
421 MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
422 MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
423 MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
424 MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
425 MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
426 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
427 MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
428 MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
430 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
431 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
433 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/
434 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/
436 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/
437 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/
439 MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)); /*I2C4_SCL*/
440 MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)); /*I2C4_SDA*/
442 MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); /*HDQ_SIO*/
444 MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)); /*McSPI1_CLK*/
445 MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)); /*McSPI1_SIMO */
446 MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)); /*McSPI1_SOMI */
447 MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)); /*McSPI1_CS0*/
448 MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)); /*GPIO_175*/
449 MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)); /*GPIO_176*/
450 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /*McSPI1_CS3*/
452 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*McSPI2_CLK*/
453 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /*McSPI2_SIMO*/
454 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*McSPI2_SOMI*/
455 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*McSPI2_CS0*/
456 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /*McSPI2_CS1*/
458 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
459 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
460 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
461 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)); /*GPIO_2*/
462 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)); /*GPIO_3 */
463 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)); /*GPIO_4*/
464 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)); /*GPIO_5*/
465 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)); /*GPIO_6*/
466 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)); /*GPIO_7*/
468 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*SYS_OFF_MODE*/
469 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*SYS_CLKOUT1*/
470 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)); /*SYS_CLKOUT2*/
472 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
473 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
474 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
475 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /*JTAG_EMU0*/
476 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /*JTAG_EMU1*/
478 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); /*ETK_CLK*/
479 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/
480 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)); /*ETK_D0*/
481 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)); /*ETK_D1*/
482 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)); /*ETK_D2*/
483 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)); /*ETK_D3*/
484 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); /*ETK_D4*/
485 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); /*ETK_D5*/
486 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); /*ETK_D6*/
487 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/
488 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/
489 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/
490 MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/
491 MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/
492 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/
493 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/
494 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/
495 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/
497 MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/
498 MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/
499 MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /*d2d_mcad3*/
500 MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /*d2d_mcad4*/
501 MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /*d2d_mcad5*/
502 MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /*d2d_mcad6*/
503 MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /*d2d_mcad7*/
504 MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /*d2d_mcad8*/
505 MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /*d2d_mcad9*/
506 MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /*d2d_mcad10*/
507 MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /*d2d_mcad11*/
508 MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /*d2d_mcad12*/
509 MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /*d2d_mcad13*/
510 MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /*d2d_mcad14*/
511 MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /*d2d_mcad15*/
512 MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /*d2d_mcad16*/
513 MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /*d2d_mcad17*/
514 MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /*d2d_mcad18*/
515 MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /*d2d_mcad19*/
516 MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /*d2d_mcad20*/
517 MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /*d2d_mcad21*/
518 MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /*d2d_mcad22*/
519 MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /*d2d_mcad23*/
520 MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /*d2d_mcad24*/
521 MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /*d2d_mcad25*/
522 MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /*d2d_mcad26*/
523 MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /*d2d_mcad27*/
524 MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /*d2d_mcad28*/
525 MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /*d2d_mcad29*/
526 MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /*d2d_mcad30*/
527 MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /*d2d_mcad31*/
528 MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /*d2d_mcad32*/
529 MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /*d2d_mcad33*/
530 MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /*d2d_mcad34*/
531 MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /*d2d_mcad35*/
532 MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /*d2d_mcad36*/
533 MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); /*d2d_clk26mi*/
534 MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); /*d2d_nrespwron*/
535 MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); /*d2d_nreswarm */
536 MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); /*d2d_arm9nirq */
537 MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); /*d2d_uma2p6fiq*/
538 MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); /*d2d_spint*/
539 MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); /*d2d_frint*/
540 MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); /*d2d_dmareq0*/
541 MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); /*d2d_dmareq1*/
542 MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); /*d2d_dmareq2*/
543 MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); /*d2d_dmareq3*/
544 MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); /*d2d_n3gtrst*/
545 MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); /*d2d_n3gtdi*/
546 MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); /*d2d_n3gtdo*/
547 MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); /*d2d_n3gtms*/
548 MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); /*d2d_n3gtck*/
549 MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); /*d2d_n3grtck*/
550 MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); /*d2d_mstdby*/
551 MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); /*d2d_swakeup*/
552 MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); /*d2d_idlereq*/
553 MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); /*d2d_idleack*/
554 MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); /*d2d_mwrite*/
555 MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); /*d2d_swrite*/
556 MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); /*d2d_mread*/
557 MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/
558 MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/
559 MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/