2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 //###CHD: es gibt eigentlich kein DDR bei uns -> weg damit!; dto. PCI!
32 #if defined(CONFIG_MPC5200_DDR)
33 #include "mt46v16m16-75.h"
35 //#include "mt48lc16m16a2-75.h"
36 #include "mt48lc8m32b2-6-7.h"
39 extern flash_info_t flash_info[]; /* FLASH chips info */
41 //###CHD: wenn RAMBOOT gehen wuerde, ....
43 static void sdram_start (int hi_addr)
45 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
47 /* unlock mode register */
48 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
49 __asm__ volatile ("sync");
51 /* precharge all banks */
52 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
53 __asm__ volatile ("sync");
56 /* set mode register: extended mode */
57 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
58 __asm__ volatile ("sync");
60 /* set mode register: reset DLL */
61 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
62 __asm__ volatile ("sync");
65 /* precharge all banks */
66 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
67 __asm__ volatile ("sync");
70 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
71 __asm__ volatile ("sync");
73 /* set mode register */
74 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
75 __asm__ volatile ("sync");
77 /* normal operation */
78 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
79 __asm__ volatile ("sync");
84 * ATTENTION: Although partially referenced initdram does NOT make real use
85 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
86 * is something else than 0x00000000.
89 #if defined(CONFIG_MPC5200)
90 long int initdram (int board_type)
97 /* setup SDRAM chip selects */
98 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
99 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
100 __asm__ volatile ("sync");
102 /* setup config registers */
103 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
104 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
105 __asm__ volatile ("sync");
109 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
110 __asm__ volatile ("sync");
113 /* find RAM size using SDRAM CS0 only */
115 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
117 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
125 /* memory smaller than 1MB is impossible */
126 if (dramsize < (1 << 20)) {
130 /* set SDRAM CS0 size according to the amount of RAM found */
132 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
134 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
137 /* let SDRAM CS1 start right after CS0 */
138 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
140 /* find RAM size using SDRAM CS1 only */
143 test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
146 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
155 /* memory smaller than 1MB is impossible */
156 if (dramsize2 < (1 << 20)) {
160 /* set SDRAM CS1 size according to the amount of RAM found */
162 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
163 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
165 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
168 #else /* CFG_RAMBOOT */
170 /* retrieve size of memory connected to SDRAM CS0 */
171 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
172 if (dramsize >= 0x13) {
173 dramsize = (1 << (dramsize - 0x13)) << 20;
178 /* retrieve size of memory connected to SDRAM CS1 */
179 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
180 if (dramsize2 >= 0x13) {
181 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
186 #endif /* CFG_RAMBOOT */
188 return dramsize + dramsize2;
191 //###CHD: sowas gibt es bei usn nicht!
192 #elif defined(CONFIG_MGT5100)
194 long int initdram (int board_type)
200 /* setup and enable SDRAM chip selects */
201 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
202 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
203 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
204 __asm__ volatile ("sync");
206 /* setup config registers */
207 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
208 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
210 /* address select register */
211 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
212 __asm__ volatile ("sync");
216 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
218 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
226 /* set SDRAM end address according to size */
227 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
229 #else /* CFG_RAMBOOT */
231 /* Retrieve amount of SDRAM available */
232 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
234 #endif /* CFG_RAMBOOT */
240 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
243 int checkboard (void)
245 puts ("Board: MCC200\n");
249 int misc_init_r (void)
251 DECLARE_GLOBAL_DATA_PTR;
254 * Adjust flash start and offset to detected values
256 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
257 gd->bd->bi_flashoffset = 0;
260 * Check if boot FLASH isn't max size
262 if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) {
264 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
265 START_REG(gd->bd->bi_flashstart);
266 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
267 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
270 * Re-check to get correct base address
272 flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
275 * Re-do flash protection upon new addresses
277 flash_protect (FLAG_PROTECT_CLEAR,
278 gd->bd->bi_flashstart, 0xffffffff,
279 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
281 /* Monitor protection ON by default */
282 flash_protect (FLAG_PROTECT_SET,
283 CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
284 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
286 /* Environment protection ON by default */
287 flash_protect (FLAG_PROTECT_SET,
289 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
290 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
292 /* Redundant environment protection ON by default */
293 flash_protect (FLAG_PROTECT_SET,
295 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
296 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
303 static struct pci_controller hose;
305 extern void pci_mpc5xxx_init(struct pci_controller *);
307 void pci_init_board(void)
309 pci_mpc5xxx_init(&hose);
313 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
315 void init_ide_reset (void)
317 debug ("init_ide_reset\n");
321 void ide_set_reset (int idereset)
323 debug ("ide_reset(%d)\n", idereset);
326 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
328 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
329 extern void doc_probe (ulong physadr);
332 doc_probe (CFG_DOC_BASE);