2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include "mt48lc8m32b2-6-7.h"
33 DECLARE_GLOBAL_DATA_PTR;
35 extern flash_info_t flash_info[]; /* FLASH chips info */
37 ulong flash_get_size (ulong base, int banknum);
40 static void sdram_start (int hi_addr)
42 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
44 /* unlock mode register */
45 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
46 __asm__ volatile ("sync");
48 /* precharge all banks */
49 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
50 __asm__ volatile ("sync");
53 /* set mode register: extended mode */
54 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
55 __asm__ volatile ("sync");
57 /* set mode register: reset DLL */
58 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
59 __asm__ volatile ("sync");
62 /* precharge all banks */
63 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
64 __asm__ volatile ("sync");
67 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
68 __asm__ volatile ("sync");
70 /* set mode register */
71 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
72 __asm__ volatile ("sync");
74 /* normal operation */
75 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
76 __asm__ volatile ("sync");
81 * ATTENTION: Although partially referenced initdram does NOT make real use
82 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
83 * is something else than 0x00000000.
86 long int initdram (int board_type)
93 /* setup SDRAM chip selects */
94 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
95 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
96 __asm__ volatile ("sync");
98 /* setup config registers */
99 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
100 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
101 __asm__ volatile ("sync");
105 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
106 __asm__ volatile ("sync");
109 /* find RAM size using SDRAM CS0 only */
111 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
113 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
121 /* memory smaller than 1MB is impossible */
122 if (dramsize < (1 << 20)) {
126 /* set SDRAM CS0 size according to the amount of RAM found */
128 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
130 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
133 /* let SDRAM CS1 start right after CS0 */
134 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
136 /* find RAM size using SDRAM CS1 only */
139 test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
142 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
151 /* memory smaller than 1MB is impossible */
152 if (dramsize2 < (1 << 20)) {
156 /* set SDRAM CS1 size according to the amount of RAM found */
158 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
159 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
161 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
164 #else /* CFG_RAMBOOT */
166 /* retrieve size of memory connected to SDRAM CS0 */
167 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
168 if (dramsize >= 0x13) {
169 dramsize = (1 << (dramsize - 0x13)) << 20;
174 /* retrieve size of memory connected to SDRAM CS1 */
175 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
176 if (dramsize2 >= 0x13) {
177 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
182 #endif /* CFG_RAMBOOT */
184 return dramsize + dramsize2;
187 int checkboard (void)
189 puts ("Board: MCC200\n");
193 int misc_init_r (void)
196 * Adjust flash start and offset to detected values
198 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
199 gd->bd->bi_flashoffset = 0;
202 * Check if boot FLASH isn't max size
204 if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) {
206 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
207 START_REG(gd->bd->bi_flashstart);
208 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
209 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
212 * Re-check to get correct base address
214 flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
217 * Re-do flash protection upon new addresses
219 flash_protect (FLAG_PROTECT_CLEAR,
220 gd->bd->bi_flashstart, 0xffffffff,
221 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
223 /* Monitor protection ON by default */
224 flash_protect (FLAG_PROTECT_SET,
225 CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
226 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
228 /* Environment protection ON by default */
229 flash_protect (FLAG_PROTECT_SET,
231 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
232 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
234 /* Redundant environment protection ON by default */
235 flash_protect (FLAG_PROTECT_SET,
237 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
238 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
241 if (gd->bd->bi_flashsize > (32 << 20)) {
242 /* Unprotect the upper bank of the Flash */
243 *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
244 flash_protect (FLAG_PROTECT_CLEAR,
245 flash_info[0].start[0] + flash_info[0].size / 2,
246 (flash_info[0].start[0] + flash_info[0].size) / 2 - 1,
248 *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
255 static struct pci_controller hose;
257 extern void pci_mpc5xxx_init(struct pci_controller *);
259 void pci_init_board(void)
261 pci_mpc5xxx_init(&hose);
265 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
267 void init_ide_reset (void)
269 debug ("init_ide_reset\n");
273 void ide_set_reset (int idereset)
275 debug ("ide_reset(%d)\n", idereset);
278 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
280 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
281 extern void doc_probe (ulong physadr);
284 doc_probe (CFG_DOC_BASE);