2 * (C) Copyright 2001-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Modified during 2001 by
6 * Advanced Communications Technologies (Australia) Pty. Ltd.
7 * Howard Walker, Tuong Vu-Dinh
9 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
10 * Added support for the 16M dram simm on the 8260ads boards
12 * (C) Copyright 2003 Arabella Software Ltd.
13 * Yuli Barcohen <yuli@arabellasw.com>
14 * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 #include <asm/m8260_pci.h>
44 * I/O Port configuration table
46 * if conf is 1, then that port pin will be configured at boot time
47 * according to the five values podr/pdir/ppar/psor/pdat for that entry
50 const iop_conf_t iop_conf_tab[4][32] = {
52 /* Port A configuration */
53 { /* conf ppar psor pdir podr pdat */
54 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
55 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
56 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
57 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
58 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
59 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
60 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
61 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
62 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
63 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
64 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
65 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
66 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
67 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
68 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
69 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
70 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
71 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
72 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
73 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
74 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
75 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
76 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
77 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
78 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
79 /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
80 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
81 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
82 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
83 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
84 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
85 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
88 /* Port B configuration */
89 { /* conf ppar psor pdir podr pdat */
90 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
91 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
92 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
93 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
94 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
95 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
96 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
97 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
98 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
99 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
100 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
101 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
102 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
103 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
104 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
105 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
106 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
107 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
108 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
109 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
110 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
111 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
112 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
113 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
114 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
115 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
116 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
117 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
118 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
119 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
120 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
121 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
125 { /* conf ppar psor pdir podr pdat */
126 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
127 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
128 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
129 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
130 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
131 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
132 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
133 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
134 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
135 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
136 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
137 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
138 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
139 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
140 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
141 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
142 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
143 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
144 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
145 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
146 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
147 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */
148 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
149 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
150 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
151 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
152 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
153 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
154 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
155 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
156 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
157 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
161 { /* conf ppar psor pdir podr pdat */
162 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
163 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
164 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
165 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
166 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
167 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
168 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
169 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
170 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
171 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
172 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
173 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
174 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
175 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
176 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
177 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
178 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
179 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
180 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
181 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
182 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
183 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
184 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
185 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
186 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
187 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
188 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
189 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
190 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
191 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
192 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
193 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
197 void reset_phy (void)
199 vu_long *bcsr = (vu_long *)CFG_BCSR;
201 /* reset the FEC port */
202 bcsr[1] &= ~FETH1_RST;
204 bcsr[1] |= FETH1_RST;
207 #if CONFIG_ADSTYPE == CFG_PQ2FADS
209 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
210 * Enable autonegotiation.
212 miiphy_write(0, 16, 0x610);
213 miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
216 * Ethernet PHY is configured (by means of configuration pins)
217 * to work at 10Mb/s only. We reconfigure it using MII
218 * to advertise all capabilities, including 100Mb/s, and
219 * restart autonegotiation.
221 miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
222 miiphy_write(0, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
223 miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
224 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
225 #endif /* CONFIG_MII */
228 int board_pre_init (void)
230 vu_long *bcsr = (vu_long *)CFG_BCSR;
232 bcsr[1] = ~FETHIEN1 & ~RS232EN_1;
234 #if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */
235 #if CONFIG_ADSTYPE == CFG_PQ2FADS
236 if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
237 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
239 volatile immap_t *immap = (immap_t *) CFG_IMMR;
241 immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
242 immap->im_siu_conf.sc_siumcr =
243 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
246 #endif /* CONFIG_ADSTYPE != CFG_8260ADS */
251 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
253 long int initdram (int board_type)
255 #if CONFIG_ADSTYPE == CFG_PQ2FADS
262 volatile immap_t *immap = (immap_t *) CFG_IMMR;
263 volatile memctl8260_t *memctl = &immap->im_memctl;
264 volatile uchar *ramaddr, c = 0xff;
271 immap->im_siu_conf.sc_ppc_acr = 0x00000002;
272 immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
273 immap->im_siu_conf.sc_tescr1 = 0x00004000;
275 memctl->memc_mptpr = CFG_MPTPR;
276 #ifdef CFG_LSDRAM_BASE
278 Initialise local bus SDRAM only if the pins
279 are configured as local bus pins and not as PCI.
280 The configuration is determined by the HRCW.
282 if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
283 memctl->memc_lsrt = CFG_LSRT;
284 #if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
285 memctl->memc_or3 = 0xFF803280;
286 memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861;
288 memctl->memc_or4 = 0xFFC01480;
289 memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
290 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
291 memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
292 ramaddr = (uchar *) CFG_LSDRAM_BASE;
294 memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
295 for (i = 0; i < 8; i++)
297 memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
299 memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
301 #endif /* CFG_LSDRAM_BASE */
303 /* Init 60x bus SDRAM */
304 #ifdef CONFIG_SPD_EEPROM
307 uint pbi, bsel, rowst, lsb, tmp;
309 i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
311 /* Bank-based interleaving is not supported for physical bank
312 sizes greater than 128MB which is encoded as 0x20 in SPD
314 pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
315 msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
316 or = ~(msize - 1) << 20; /* SDAM */
317 switch (spd.nbanks) { /* BPD */
330 lsb = 3; /* For 64-bit port, lsb is 3 bits */
332 if (pbi) { /* Bus partition depends on interleaving */
333 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
334 or |= (rowst << 9); /* ROWST */
336 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
337 or |= ((rowst * 2 - 12) << 9); /* ROWST */
339 or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
341 psdmr = (pbi << 31); /* PBI */
342 /* Bus multiplexing parameters */
343 tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
344 psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
345 psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
347 tmp = (31 - lsb - 10) - tmp;
348 /* Pin connected to SDA10 is (31 - lsb - 10).
349 rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
350 so (rowst + tmp) alternates with AP.
352 if (pbi) /* Table 10-7 */
353 psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
355 psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
357 /* SDRAM device-specific parameters */
358 tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
359 switch (tmp) { /* RFRC */
370 psdmr |= ((tmp - 2) << 15);
375 psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
376 psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
377 /* BL=0 because for 64-bit SDRAM burst length must be 4 */
379 for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
381 switch (i) { /* WRC */
391 /* EAMUX=0 - no external address multiplexing */
392 /* BUFCMD=0 - no external buffers */
393 for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
397 switch (spd.refresh & 0x7F) {
416 psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
417 ((memctl->memc_mptpr >> 8) + 1)) - 1;
419 printf ("\nDIMM type: %-18.18s\n", spd.mpart);
420 printf ("SPD size: %d\n", spd.info_size);
421 printf ("EEPROM size: %d\n", 1 << spd.chip_size);
422 printf ("Memory type: %d\n", spd.mem_type);
423 printf ("Row addr: %d\n", spd.nrow_addr);
424 printf ("Column addr: %d\n", spd.ncol_addr);
425 printf ("# of rows: %d\n", spd.nrows);
426 printf ("Row density: %d\n", spd.row_dens);
427 printf ("# of banks: %d\n", spd.nbanks);
428 printf ("Data width: %d\n",
429 256 * spd.dataw_msb + spd.dataw_lsb);
430 printf ("Chip width: %d\n", spd.primw);
431 printf ("Refresh rate: %02X\n", spd.refresh);
432 printf ("CAS latencies: %02X\n", spd.cas_lat);
433 printf ("Write latencies: %02X\n", spd.write_lat);
434 printf ("tRP: %d\n", spd.trp);
435 printf ("tRCD: %d\n", spd.trcd);
437 printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
438 #endif /* SPD_DEBUG */
440 #else /* !CONFIG_SPD_EEPROM */
444 #endif /* CONFIG_SPD_EEPROM */
445 memctl->memc_psrt = psrt;
446 memctl->memc_or2 = or;
447 memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
448 ramaddr = (uchar *) CFG_SDRAM_BASE;
449 memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
451 memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
452 for (i = 0; i < 8; i++)
455 memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
457 memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
459 #endif /* CFG_RAMBOOT */
461 /* return total 60x bus SDRAM size */
462 return (msize * 1024 * 1024);
465 int checkboard (void)
467 #if CONFIG_ADSTYPE == CFG_8260ADS
468 puts ("Board: Motorola MPC8260ADS\n");
469 #elif CONFIG_ADSTYPE == CFG_8266ADS
470 puts ("Board: Motorola MPC8266ADS\n");
471 #elif CONFIG_ADSTYPE == CFG_PQ2FADS
472 puts ("Board: Motorola PQ2FADS-ZU\n");
474 puts ("Board: unknown\n");