2 * See file CREDITS for list of people who contributed to this
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/global_data.h>
30 /* System RAM mapped to PCI space */
31 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
32 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
34 #ifndef CONFIG_PCI_PNP
35 static struct pci_config_table pci_mpc83xxads_config_table[] = {
36 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
37 PCI_IDSEL_NUMBER, PCI_ANY_ID,
38 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
40 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
47 static struct pci_controller pci_hose[] = {
49 #ifndef CONFIG_PCI_PNP
50 config_table:pci_mpc83xxads_config_table,
54 #ifndef CONFIG_PCI_PNP
55 config_table:pci_mpc83xxads_config_table,
60 /**************************************************************************
62 * pib_init() -- initialize the PCA9555PW IO expander on the PIB board
70 * Assign PIB PMC slot to desired PCI bus
72 mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
73 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
76 i2c_write(0x23, 0x6, 1, &val8, 1);
77 i2c_write(0x23, 0x7, 1, &val8, 1);
79 i2c_write(0x23, 0x2, 1, &val8, 1);
80 i2c_write(0x23, 0x3, 1, &val8, 1);
83 i2c_write(0x26, 0x6, 1, &val8, 1);
85 i2c_write(0x26, 0x7, 1, &val8, 1);
86 #if defined(PCI_64BIT)
87 val8 = 0xf4; /* PMC2:PCI1/64-bit */
88 #elif defined(PCI_ALL_PCI1)
89 val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
90 #elif defined(PCI_ONE_PCI1)
91 val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
93 val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
95 i2c_write(0x26, 0x2, 1, &val8, 1);
97 i2c_write(0x26, 0x3, 1, &val8, 1);
99 i2c_write(0x27, 0x6, 1, &val8, 1);
100 i2c_write(0x27, 0x7, 1, &val8, 1);
102 i2c_write(0x27, 0x2, 1, &val8, 1);
104 i2c_write(0x27, 0x3, 1, &val8, 1);
107 #if defined(PCI_64BIT)
108 printf("PCI1: 64-bit on PMC2\n");
109 #elif defined(PCI_ALL_PCI1)
110 printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
111 #elif defined(PCI_ONE_PCI1)
112 printf("PCI1: 32-bit on PMC1\n");
113 printf("PCI2: 32-bit on PMC2, PMC3\n");
115 printf("PCI1: 32-bit on PMC1, PMC2\n");
116 printf("PCI2: 32-bit on PMC3\n");
120 /**************************************************************************
123 * NOTICE: PCI2 is not currently supported
129 DECLARE_GLOBAL_DATA_PTR;
130 volatile immap_t * immr;
131 volatile clk8349_t * clk;
132 volatile law8349_t * pci_law;
133 volatile pot8349_t * pci_pot;
134 volatile pcictrl8349_t * pci_ctrl;
135 volatile pciconf8349_t * pci_conf;
138 struct pci_controller * hose;
140 immr = (immap_t *)CFG_IMMRBAR;
141 clk = (clk8349_t *)&immr->clk;
142 pci_law = immr->sysconf.pcilaw;
143 pci_pot = immr->ios.pot;
144 pci_ctrl = immr->pci_ctrl;
145 pci_conf = immr->pci_conf;
152 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
157 clk->occr = 0xff000000;
161 * Release PCI RST Output signal
169 * Configure PCI Local Access Windows
171 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
172 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
174 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
175 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
178 * Configure PCI Outbound Translation Windows
182 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
183 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
184 pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
187 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
188 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
189 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
192 * Configure PCI Inbound Translation Windows
195 /* we need RAM mapped to PCI space for the devices to
196 * access main memory */
197 pci_ctrl[0].pitar1 = 0x0;
198 pci_ctrl[0].pibar1 = 0x0;
199 pci_ctrl[0].piebar1 = 0x0;
200 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
202 hose->first_busno = 0;
203 hose->last_busno = 0xff;
205 /* PCI memory space */
206 pci_set_region(hose->regions + 0,
213 pci_set_region(hose->regions + 1,
219 /* System memory space */
220 pci_set_region(hose->regions + 2,
221 CONFIG_PCI_SYS_MEM_BUS,
222 CONFIG_PCI_SYS_MEM_PHYS,
224 PCI_REGION_MEM | PCI_REGION_MEMORY);
226 hose->region_count = 3;
228 pci_setup_indirect(hose,
229 (CFG_IMMRBAR+0x8300),
230 (CFG_IMMRBAR+0x8304));
232 pci_register_hose(hose);
235 * Write to Command register
238 pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
240 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
241 pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
245 * Clear non-reserved bits in status register.
247 pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
249 pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
252 #ifdef CONFIG_PCI_SCAN_SHOW
253 printf("PCI: Bus Dev VenId DevId Class Int\n");
258 hose->last_busno = pci_hose_scan(hose);
260 #endif /* CONFIG_PCI */