3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/mpc8349_pci.h>
33 #if defined(CONFIG_SPD_EEPROM)
34 #include <spd_sdram.h>
36 #if defined(CONFIG_OF_FLAT_TREE)
40 int fixed_sdram(void);
41 void sdram_init(void);
43 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
44 void ddr_enable_ecc(unsigned int dram_size);
47 int board_early_init_f (void)
49 volatile u8* bcsr = (volatile u8*)CFG_BCSR;
51 /* Enable flash write */
54 #ifdef CFG_USE_MPC834XSYS_USB_PHY
55 /* Use USB PHY on SYS board */
62 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
64 long int initdram (int board_type)
66 volatile immap_t *im = (immap_t *)CFG_IMMR;
69 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
72 puts("Initializing\n");
74 /* DDR SDRAM - Main SODIMM */
75 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
76 #if defined(CONFIG_SPD_EEPROM)
79 msize = fixed_sdram();
82 * Initialize SDRAM if it is on local bus.
86 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
88 * Initialize and enable DDR ECC.
90 ddr_enable_ecc(msize * 1024 * 1024);
93 /* return total bus SDRAM size(bytes) -- DDR */
94 return (msize * 1024 * 1024);
97 #if !defined(CONFIG_SPD_EEPROM)
98 /*************************************************************************
99 * fixed sdram init -- doesn't use serial presence detect.
100 ************************************************************************/
101 int fixed_sdram(void)
103 volatile immap_t *im = (immap_t *)CFG_IMMR;
108 msize = CFG_DDR_SIZE;
109 for (ddr_size = msize << 20, ddr_size_log2 = 0;
111 ddr_size = ddr_size>>1, ddr_size_log2++) {
116 im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
117 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
119 #if (CFG_DDR_SIZE != 256)
120 #warning Currenly any ddr size other than 256 is not supported
122 im->ddr.csbnds[2].csbnds = 0x0000000f;
123 im->ddr.cs_config[2] = CFG_DDR_CONFIG;
125 /* currently we use only one CS, so disable the other banks */
126 im->ddr.cs_config[0] = 0;
127 im->ddr.cs_config[1] = 0;
128 im->ddr.cs_config[3] = 0;
130 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
131 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
135 #if defined(CONFIG_DDR_2T_TIMING)
138 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
139 #if defined (CONFIG_DDR_32BIT)
140 /* for 32-bit mode burst length is 8 */
141 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
143 im->ddr.sdram_mode = CFG_DDR_MODE;
145 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
148 /* enable DDR controller */
149 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
152 #endif/*!CFG_SPD_EEPROM*/
155 int checkboard (void)
157 puts("Board: Freescale MPC8349EMDS\n");
162 * if MPC8349EMDS is soldered with SDRAM
164 #if defined(CFG_BR2_PRELIM) \
165 && defined(CFG_OR2_PRELIM) \
166 && defined(CFG_LBLAWBAR2_PRELIM) \
167 && defined(CFG_LBLAWAR2_PRELIM)
169 * Initialize SDRAM memory on the Local Bus.
172 void sdram_init(void)
174 volatile immap_t *immap = (immap_t *)CFG_IMMR;
175 volatile lbus83xx_t *lbc= &immap->lbus;
176 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
178 puts("\n SDRAM on Local Bus: ");
179 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
182 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
185 /* setup mtrpt, lsrt and lbcr for LB bus */
186 lbc->lbcr = CFG_LBC_LBCR;
187 lbc->mrtpr = CFG_LBC_MRTPR;
188 lbc->lsrt = CFG_LBC_LSRT;
192 * Configure the SDRAM controller Machine Mode Register.
194 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
196 lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
201 lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
228 /* 0x58636733; mode register write operation */
229 lbc->lsdmr = CFG_LBC_LSDMR_4;
234 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
240 void sdram_init(void)
242 put("SDRAM on Local Bus is NOT available!\n");
246 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
250 void ecc_print_status(void)
252 volatile immap_t *immap = (immap_t *)CFG_IMMR;
253 volatile ddr83xx_t *ddr = &immap->ddr;
255 printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
258 printf("Memory Error Interrupt Enable:\n");
259 printf(" Multiple-Bit Error Interrupt Enable: %d\n",
260 (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
261 printf(" Single-Bit Error Interrupt Enable: %d\n",
262 (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
263 printf(" Memory Select Error Interrupt Enable: %d\n\n",
264 (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
267 printf("Memory Error Disable:\n");
268 printf(" Multiple-Bit Error Disable: %d\n",
269 (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
270 printf(" Sinle-Bit Error Disable: %d\n",
271 (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
272 printf(" Memory Select Error Disable: %d\n\n",
273 (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
275 /* Error injection */
276 printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
277 ddr->data_err_inject_hi, ddr->data_err_inject_lo);
279 printf("Memory Data Path Error Injection Mask ECC:\n");
280 printf(" ECC Mirror Byte: %d\n",
281 (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
282 printf(" ECC Injection Enable: %d\n",
283 (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
284 printf(" ECC Error Injection Mask: 0x%02x\n\n",
285 ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
287 /* SBE counter/threshold */
288 printf("Memory Single-Bit Error Management (0..255):\n");
289 printf(" Single-Bit Error Threshold: %d\n",
290 (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
291 printf(" Single-Bit Error Counter: %d\n\n",
292 (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
295 printf("Memory Error Detect:\n");
296 printf(" Multiple Memory Errors: %d\n",
297 (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
298 printf(" Multiple-Bit Error: %d\n",
299 (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
300 printf(" Single-Bit Error: %d\n",
301 (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
302 printf(" Memory Select Error: %d\n\n",
303 (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
306 printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
307 printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
308 ddr->capture_data_hi, ddr->capture_data_lo);
309 printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
310 ddr->capture_ecc & CAPTURE_ECC_ECE);
312 printf("Memory Error Attributes Capture:\n");
313 printf(" Data Beat Number: %d\n",
314 (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
315 printf(" Transaction Size: %d\n",
316 (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
317 printf(" Transaction Source: %d\n",
318 (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
319 printf(" Transaction Type: %d\n",
320 (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
321 printf(" Error Information Valid: %d\n\n",
322 ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
325 int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
327 volatile immap_t *immap = (immap_t *)CFG_IMMR;
328 volatile ddr83xx_t *ddr = &immap->ddr;
330 u64 *addr, count, val64;
334 printf ("Usage:\n%s\n", cmdtp->usage);
339 if (strcmp(argv[1], "status") == 0) {
342 } else if (strcmp(argv[1], "captureclear") == 0) {
343 ddr->capture_address = 0;
344 ddr->capture_data_hi = 0;
345 ddr->capture_data_lo = 0;
346 ddr->capture_ecc = 0;
347 ddr->capture_attributes = 0;
353 if (strcmp(argv[1], "sbecnt") == 0) {
354 val = simple_strtoul(argv[2], NULL, 10);
356 printf("Incorrect Counter value, should be 0..255\n");
360 val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
361 val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
365 } else if (strcmp(argv[1], "sbethr") == 0) {
366 val = simple_strtoul(argv[2], NULL, 10);
368 printf("Incorrect Counter value, should be 0..255\n");
372 val = (val << ECC_ERROR_MAN_SBET_SHIFT);
373 val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
377 } else if (strcmp(argv[1], "errdisable") == 0) {
378 val = ddr->err_disable;
380 if (strcmp(argv[2], "+sbe") == 0) {
381 val |= ECC_ERROR_DISABLE_SBED;
382 } else if (strcmp(argv[2], "+mbe") == 0) {
383 val |= ECC_ERROR_DISABLE_MBED;
384 } else if (strcmp(argv[2], "+mse") == 0) {
385 val |= ECC_ERROR_DISABLE_MSED;
386 } else if (strcmp(argv[2], "+all") == 0) {
387 val |= (ECC_ERROR_DISABLE_SBED |
388 ECC_ERROR_DISABLE_MBED |
389 ECC_ERROR_DISABLE_MSED);
390 } else if (strcmp(argv[2], "-sbe") == 0) {
391 val &= ~ECC_ERROR_DISABLE_SBED;
392 } else if (strcmp(argv[2], "-mbe") == 0) {
393 val &= ~ECC_ERROR_DISABLE_MBED;
394 } else if (strcmp(argv[2], "-mse") == 0) {
395 val &= ~ECC_ERROR_DISABLE_MSED;
396 } else if (strcmp(argv[2], "-all") == 0) {
397 val &= ~(ECC_ERROR_DISABLE_SBED |
398 ECC_ERROR_DISABLE_MBED |
399 ECC_ERROR_DISABLE_MSED);
401 printf("Incorrect err_disable field\n");
405 ddr->err_disable = val;
406 __asm__ __volatile__ ("sync");
407 __asm__ __volatile__ ("isync");
409 } else if (strcmp(argv[1], "errdetectclr") == 0) {
410 val = ddr->err_detect;
412 if (strcmp(argv[2], "mme") == 0) {
413 val |= ECC_ERROR_DETECT_MME;
414 } else if (strcmp(argv[2], "sbe") == 0) {
415 val |= ECC_ERROR_DETECT_SBE;
416 } else if (strcmp(argv[2], "mbe") == 0) {
417 val |= ECC_ERROR_DETECT_MBE;
418 } else if (strcmp(argv[2], "mse") == 0) {
419 val |= ECC_ERROR_DETECT_MSE;
420 } else if (strcmp(argv[2], "all") == 0) {
421 val |= (ECC_ERROR_DETECT_MME |
422 ECC_ERROR_DETECT_MBE |
423 ECC_ERROR_DETECT_SBE |
424 ECC_ERROR_DETECT_MSE);
426 printf("Incorrect err_detect field\n");
430 ddr->err_detect = val;
432 } else if (strcmp(argv[1], "injectdatahi") == 0) {
433 val = simple_strtoul(argv[2], NULL, 16);
435 ddr->data_err_inject_hi = val;
437 } else if (strcmp(argv[1], "injectdatalo") == 0) {
438 val = simple_strtoul(argv[2], NULL, 16);
440 ddr->data_err_inject_lo = val;
442 } else if (strcmp(argv[1], "injectecc") == 0) {
443 val = simple_strtoul(argv[2], NULL, 16);
445 printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
448 val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
450 ddr->ecc_err_inject = val;
452 } else if (strcmp(argv[1], "inject") == 0) {
453 val = ddr->ecc_err_inject;
455 if (strcmp(argv[2], "en") == 0)
456 val |= ECC_ERR_INJECT_EIEN;
457 else if (strcmp(argv[2], "dis") == 0)
458 val &= ~ECC_ERR_INJECT_EIEN;
460 printf("Incorrect command\n");
462 ddr->ecc_err_inject = val;
463 __asm__ __volatile__ ("sync");
464 __asm__ __volatile__ ("isync");
466 } else if (strcmp(argv[1], "mirror") == 0) {
467 val = ddr->ecc_err_inject;
469 if (strcmp(argv[2], "en") == 0)
470 val |= ECC_ERR_INJECT_EMB;
471 else if (strcmp(argv[2], "dis") == 0)
472 val &= ~ECC_ERR_INJECT_EMB;
474 printf("Incorrect command\n");
476 ddr->ecc_err_inject = val;
482 if (strcmp(argv[1], "test") == 0) {
483 addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
484 count = simple_strtoul(argv[3], NULL, 16);
487 printf("Address not alligned on double word boundary\n");
491 disable_interrupts();
494 for (i = addr; i < addr + count; i++) {
496 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
497 __asm__ __volatile__ ("sync");
498 __asm__ __volatile__ ("isync");
500 /* write memory location injecting errors */
501 *i = 0x1122334455667788ULL;
502 __asm__ __volatile__ ("sync");
504 /* disable injects */
505 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
506 __asm__ __volatile__ ("sync");
507 __asm__ __volatile__ ("isync");
509 /* read data, this generates ECC error */
511 __asm__ __volatile__ ("sync");
513 /* disable errors for ECC */
514 ddr->err_disable |= ~ECC_ERROR_ENABLE;
515 __asm__ __volatile__ ("sync");
516 __asm__ __volatile__ ("isync");
518 /* re-initialize memory, write the location again
519 * NOT injecting errors this time */
520 *i = 0xcafecafecafecafeULL;
521 __asm__ __volatile__ ("sync");
523 /* enable errors for ECC */
524 ddr->err_disable &= ECC_ERROR_ENABLE;
525 __asm__ __volatile__ ("sync");
526 __asm__ __volatile__ ("isync");
536 printf ("Usage:\n%s\n", cmdtp->usage);
542 "ecc - support for DDR ECC features\n",
543 "status - print out status info\n"
544 "ecc captureclear - clear capture regs data\n"
545 "ecc sbecnt <val> - set Single-Bit Error counter\n"
546 "ecc sbethr <val> - set Single-Bit Threshold\n"
547 "ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
548 " [-|+]sbe - Single-Bit Error\n"
549 " [-|+]mbe - Multiple-Bit Error\n"
550 " [-|+]mse - Memory Select Error\n"
551 " [-|+]all - all errors\n"
552 "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
553 " mme - Multiple Memory Errors\n"
554 " sbe - Single-Bit Error\n"
555 " mbe - Multiple-Bit Error\n"
556 " mse - Memory Select Error\n"
557 " all - all errors\n"
558 "ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
559 "ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
560 "ecc injectecc <ecc> - set ECC Error Injection Mask\n"
561 "ecc inject <en|dis> - enable/disable error injection\n"
562 "ecc mirror <en|dis> - enable/disable mirror byte\n"
563 "ecc test <addr> <cnt> - test mem region:\n"
564 " - enables injects\n"
565 " - writes pattern injecting errors\n"
566 " - disables injects\n"
567 " - reads pattern back, generates error\n"
570 #endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
572 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
574 ft_board_setup(void *blob, bd_t *bd)
580 ft_pci_setup(blob, bd);
582 ft_cpu_setup(blob, bd);
584 p = ft_get_prop(blob, "/memory/reg", &len);
586 *p++ = cpu_to_be32(bd->bi_memstart);
587 *p = cpu_to_be32(bd->bi_memsize);