2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/global_data.h>
30 #include <asm/mpc8349_pci.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 /* System RAM mapped to PCI space */
36 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
37 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
39 #ifndef CONFIG_PCI_PNP
40 static struct pci_config_table pci_mpc8349itx_config_table[] = {
48 pci_cfgfunc_config_device,
52 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
58 static struct pci_controller pci_hose[] = {
60 #ifndef CONFIG_PCI_PNP
61 config_table:pci_mpc8349itx_config_table,
65 #ifndef CONFIG_PCI_PNP
66 config_table:pci_mpc8349itx_config_table,
71 /**************************************************************************
74 * NOTICE: PCI2 is not currently supported
77 void pci_init_board(void)
79 volatile immap_t *immr;
80 volatile clk83xx_t *clk;
81 volatile law83xx_t *pci_law;
82 volatile pot83xx_t *pci_pot;
83 volatile pcictrl83xx_t *pci_ctrl;
84 volatile pciconf83xx_t *pci_conf;
89 struct pci_controller *hose;
91 immr = (immap_t *) CFG_IMMRBAR;
92 clk = (clk83xx_t *) & immr->clk;
93 pci_law = immr->sysconf.pcilaw;
94 pci_pot = immr->ios.pot;
95 pci_ctrl = immr->pci_ctrl;
96 pci_conf = immr->pci_conf;
101 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
107 #ifdef CONFIG_HARD_I2C
108 i2c_set_bus_num(I2C_BUS_2);
109 /* Read the PCI_M66EN jumper setting */
110 if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) ||
111 (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) {
112 if (reg8 & I2C_8574_PCI66)
113 clk->occr = 0xff000000; /* 66 MHz PCI */
115 clk->occr = 0xff600001; /* 33 MHz PCI */
117 clk->occr = 0xff600001; /* 33 MHz PCI */
120 clk->occr = 0xff000000; /* 66 MHz PCI */
126 * Release PCI RST Output signal
132 #ifdef CONFIG_MPC83XX_PCI2
138 /* We need to wait at least a 1sec based on PCI specs */
142 for (i = 0; i < 1000; i++)
147 * Configure PCI Local Access Windows
149 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
150 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
152 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
153 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
156 * Configure PCI Outbound Translation Windows
159 /* PCI1 mem space - prefetch */
160 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
161 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
163 POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
166 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
167 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
168 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
170 /* PCI1 mmio - non-prefetch mem space */
171 pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
172 pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
173 pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
176 * Configure PCI Inbound Translation Windows
179 /* we need RAM mapped to PCI space for the devices to
180 * access main memory */
181 pci_ctrl[0].pitar1 = 0x0;
182 pci_ctrl[0].pibar1 = 0x0;
183 pci_ctrl[0].piebar1 = 0x0;
184 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
185 PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
187 hose->first_busno = 0;
188 hose->last_busno = 0xff;
190 /* PCI memory prefetch space */
191 pci_set_region(hose->regions + 0,
194 CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
196 /* PCI memory space */
197 pci_set_region(hose->regions + 1,
199 CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM);
202 pci_set_region(hose->regions + 2,
204 CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
206 /* System memory space */
207 pci_set_region(hose->regions + 3,
208 CONFIG_PCI_SYS_MEM_BUS,
209 CONFIG_PCI_SYS_MEM_PHYS,
210 gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
212 hose->region_count = 4;
214 pci_setup_indirect(hose,
215 (CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304));
217 pci_register_hose(hose);
220 * Write to Command register
223 dev = PCI_BDF(hose->first_busno, 0, 0);
224 pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
225 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
226 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
229 * Clear non-reserved bits in status register.
231 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
232 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
233 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
235 #ifdef CONFIG_PCI_SCAN_SHOW
236 printf("PCI: Bus Dev VenId DevId Class Int\n");
241 hose->last_busno = pci_hose_scan(hose);
243 #ifdef CONFIG_MPC83XX_PCI2
247 * Configure PCI Outbound Translation Windows
250 /* PCI2 mem space - prefetch */
251 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
252 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
254 POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M &
258 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
259 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
261 POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
263 /* PCI2 mmio - non-prefetch mem space */
264 pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
265 pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
267 POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
270 * Configure PCI Inbound Translation Windows
273 /* we need RAM mapped to PCI space for the devices to
274 * access main memory */
275 pci_ctrl[1].pitar1 = 0x0;
276 pci_ctrl[1].pibar1 = 0x0;
277 pci_ctrl[1].piebar1 = 0x0;
279 PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
280 (__ilog2(gd->ram_size) - 1);
282 hose->first_busno = pci_hose[0].last_busno + 1;
283 hose->last_busno = 0xff;
285 /* PCI memory prefetch space */
286 pci_set_region(hose->regions + 0,
289 CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
291 /* PCI memory space */
292 pci_set_region(hose->regions + 1,
294 CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM);
297 pci_set_region(hose->regions + 2,
299 CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO);
301 /* System memory space */
302 pci_set_region(hose->regions + 3,
303 CONFIG_PCI_SYS_MEM_BUS,
304 CONFIG_PCI_SYS_MEM_PHYS,
305 gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
307 hose->region_count = 4;
309 pci_setup_indirect(hose,
310 (CFG_IMMRBAR + 0x8380), (CFG_IMMRBAR + 0x8384));
312 pci_register_hose(hose);
315 * Write to Command register
318 dev = PCI_BDF(hose->first_busno, 0, 0);
319 pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
320 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
321 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
324 * Clear non-reserved bits in status register.
326 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
327 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
328 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
333 hose->last_busno = pci_hose_scan(hose);
337 #endif /* CONFIG_PCI */