2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/global_data.h>
30 #include <asm/mpc8349_pci.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 /* System RAM mapped to PCI space */
36 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
37 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
39 #ifndef CONFIG_PCI_PNP
40 static struct pci_config_table pci_mpc8349itx_config_table[] = {
48 pci_cfgfunc_config_device,
52 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
58 static struct pci_controller pci_hose[] = {
60 #ifndef CONFIG_PCI_PNP
61 config_table:pci_mpc8349itx_config_table,
65 #ifndef CONFIG_PCI_PNP
66 config_table:pci_mpc8349itx_config_table,
71 /**************************************************************************
74 * NOTICE: PCI2 is not currently supported
77 void pci_init_board(void)
79 volatile immap_t *immr;
80 volatile clk83xx_t *clk;
81 volatile law83xx_t *pci_law;
82 volatile pot83xx_t *pci_pot;
83 volatile pcictrl83xx_t *pci_ctrl;
84 volatile pciconf83xx_t *pci_conf;
89 struct pci_controller *hose;
91 immr = (immap_t *) CFG_IMMRBAR;
92 clk = (clk83xx_t *) & immr->clk;
93 pci_law = immr->sysconf.pcilaw;
94 pci_pot = immr->ios.pot;
95 pci_ctrl = immr->pci_ctrl;
96 pci_conf = immr->pci_conf;
101 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
107 #ifdef CONFIG_HARD_I2C
109 /* Read the PCI_M66EN jumper setting */
110 if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) ||
111 (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) {
112 if (reg8 & I2C_8574_PCI66)
113 clk->occr = 0xff000000; /* 66 MHz PCI */
115 clk->occr = 0xff600001; /* 33 MHz PCI */
117 clk->occr = 0xff600001; /* 33 MHz PCI */
120 clk->occr = 0xff000000; /* 66 MHz PCI */
126 * Release PCI RST Output signal
132 #ifdef CONFIG_MPC83XX_PCI2
138 /* We need to wait at least a 1sec based on PCI specs */
142 for (i = 0; i < 1000; i++)
147 * Configure PCI Local Access Windows
149 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
150 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
152 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
153 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
156 * Configure PCI Outbound Translation Windows
159 /* PCI1 mem space - prefetch */
160 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
161 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
162 pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M;
165 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
166 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
167 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
169 /* PCI1 mmio - non-prefetch mem space */
170 pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
171 pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
172 pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
175 * Configure PCI Inbound Translation Windows
178 /* we need RAM mapped to PCI space for the devices to
179 * access main memory */
180 pci_ctrl[0].pitar1 = 0x0;
181 pci_ctrl[0].pibar1 = 0x0;
182 pci_ctrl[0].piebar1 = 0x0;
183 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
184 PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
186 hose->first_busno = 0;
187 hose->last_busno = 0xff;
189 /* PCI memory prefetch space */
190 pci_set_region(hose->regions + 0,
193 CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
195 /* PCI memory space */
196 pci_set_region(hose->regions + 1,
198 CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM);
201 pci_set_region(hose->regions + 2,
203 CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
205 /* System memory space */
206 pci_set_region(hose->regions + 3,
207 CONFIG_PCI_SYS_MEM_BUS,
208 CONFIG_PCI_SYS_MEM_PHYS,
209 gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
211 hose->region_count = 4;
213 pci_setup_indirect(hose,
214 (CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304));
216 pci_register_hose(hose);
219 * Write to Command register
222 dev = PCI_BDF(hose->first_busno, 0, 0);
223 pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
224 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
225 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
228 * Clear non-reserved bits in status register.
230 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
231 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
232 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
234 #ifdef CONFIG_PCI_SCAN_SHOW
235 printf("PCI: Bus Dev VenId DevId Class Int\n");
240 hose->last_busno = pci_hose_scan(hose);
242 #ifdef CONFIG_MPC83XX_PCI2
246 * Configure PCI Outbound Translation Windows
249 /* PCI2 mem space - prefetch */
250 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
251 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
252 pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M;
255 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
256 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
257 pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M;
259 /* PCI2 mmio - non-prefetch mem space */
260 pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
261 pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
262 pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M;
265 * Configure PCI Inbound Translation Windows
268 /* we need RAM mapped to PCI space for the devices to
269 * access main memory */
270 pci_ctrl[1].pitar1 = 0x0;
271 pci_ctrl[1].pibar1 = 0x0;
272 pci_ctrl[1].piebar1 = 0x0;
274 PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
275 (__ilog2(gd->ram_size) - 1);
277 hose->first_busno = pci_hose[0].last_busno + 1;
278 hose->last_busno = 0xff;
280 /* PCI memory prefetch space */
281 pci_set_region(hose->regions + 0,
284 CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
286 /* PCI memory space */
287 pci_set_region(hose->regions + 1,
289 CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM);
292 pci_set_region(hose->regions + 2,
294 CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO);
296 /* System memory space */
297 pci_set_region(hose->regions + 3,
298 CONFIG_PCI_SYS_MEM_BUS,
299 CONFIG_PCI_SYS_MEM_PHYS,
300 gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
302 hose->region_count = 4;
304 pci_setup_indirect(hose,
305 (CFG_IMMRBAR + 0x8380), (CFG_IMMRBAR + 0x8384));
307 pci_register_hose(hose);
310 * Write to Command register
313 dev = PCI_BDF(hose->first_busno, 0, 0);
314 pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
315 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
316 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
319 * Clear non-reserved bits in status register.
321 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
322 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
323 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
328 hose->last_busno = pci_hose_scan(hose);
332 #endif /* CONFIG_PCI */
333 #ifdef CONFIG_OF_FLAT_TREE
335 ft_pci_setup(void *blob, bd_t *bd)
340 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
342 p[0] = pci_hose[0].first_busno;
343 p[1] = pci_hose[0].last_busno;
346 #ifdef CONFIG_MPC83XX_PCI2
347 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
349 p[0] = pci_hose[1].first_busno;
350 p[1] = pci_hose[1].last_busno;
354 #endif /* CONFIG_OF_FLAT_TREE */