2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
14 * PCI Configuration space access support for MPC83xx PCI Bridge
24 DECLARE_GLOBAL_DATA_PTR;
26 #if defined(CONFIG_PCI)
27 #define PCI_FUNCTION_CONFIG 0x44
28 #define PCI_FUNCTION_CFG_LOCK 0x20
31 * Initialize PCI Devices, report devices found
33 #ifndef CONFIG_PCI_PNP
34 static struct pci_config_table pci_mpc83xxemds_config_table[] = {
36 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
37 pci_cfgfunc_config_device,
40 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
45 static struct pci_controller hose[] = {
47 #ifndef CONFIG_PCI_PNP
48 config_table:pci_mpc83xxemds_config_table,
53 /**********************************************************************
55 *********************************************************************/
56 void pci_init_board(void)
57 #ifdef CONFIG_PCISLAVE
60 volatile immap_t *immr;
61 volatile law83xx_t *pci_law;
62 volatile pot83xx_t *pci_pot;
63 volatile pcictrl83xx_t *pci_ctrl;
64 volatile pciconf83xx_t *pci_conf;
66 immr = (immap_t *) CFG_IMMRBAR;
67 pci_law = immr->sysconf.pcilaw;
68 pci_pot = immr->ios.pot;
69 pci_ctrl = immr->pci_ctrl;
70 pci_conf = immr->pci_conf;
72 * Configure PCI Inbound Translation Windows
74 pci_ctrl[0].pitar0 = 0x0;
75 pci_ctrl[0].pibar0 = 0x0;
76 pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
77 PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
79 pci_ctrl[0].pitar1 = 0x0;
80 pci_ctrl[0].pibar1 = 0x0;
81 pci_ctrl[0].piebar1 = 0x0;
82 pci_ctrl[0].piwar1 &= ~PIWAR_EN;
84 pci_ctrl[0].pitar2 = 0x0;
85 pci_ctrl[0].pibar2 = 0x0;
86 pci_ctrl[0].piebar2 = 0x0;
87 pci_ctrl[0].piwar2 &= ~PIWAR_EN;
89 hose[0].first_busno = 0;
90 hose[0].last_busno = 0xff;
91 pci_setup_indirect(&hose[0],
92 (CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304));
95 pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
97 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY;
98 pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
102 * Clear non-reserved bits in status register.
104 pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
106 pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
107 PCI_LATENCY_TIMER, 0x80);
110 * Unlock configuration lock in PCI function configuration register.
112 pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
113 PCI_FUNCTION_CONFIG, ®16);
114 reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
115 pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
116 PCI_FUNCTION_CONFIG, reg16);
118 printf("Enabled PCI 32bit Agent Mode\n");
122 volatile immap_t *immr;
123 volatile clk83xx_t *clk;
124 volatile law83xx_t *pci_law;
125 volatile pot83xx_t *pci_pot;
126 volatile pcictrl83xx_t *pci_ctrl;
127 volatile pciconf83xx_t *pci_conf;
129 u8 val8, orig_i2c_bus;
134 immr = (immap_t *) CFG_IMMRBAR;
135 clk = (clk83xx_t *) & immr->clk;
136 pci_law = immr->sysconf.pcilaw;
137 pci_pot = immr->ios.pot;
138 pci_ctrl = immr->pci_ctrl;
139 pci_conf = immr->pci_conf;
141 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
146 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
147 printf("PCI clock is 66MHz\n");
148 #elif defined(PCI_33M)
149 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
150 OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
151 printf("PCI clock is 33MHz\n");
153 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
154 printf("PCI clock is 66MHz\n");
159 * Configure PCI Local Access Windows
161 pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
162 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
164 pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
165 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
168 * Configure PCI Outbound Translation Windows
171 /* PCI mem space - prefetch */
172 pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
173 pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
175 POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
177 /* PCI mmio - non-prefetch mem space */
178 pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
179 pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
180 pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
183 pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
184 pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
185 pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
188 * Configure PCI Inbound Translation Windows
190 pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
191 pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
192 pci_ctrl[0].piebar1 = 0x0;
194 PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
198 * Assign PIB PMC slot to desired PCI bus
201 mpc83xx_i2c = (i2c_t *) (CFG_IMMRBAR + CFG_I2C2_OFFSET);
202 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
205 i2c_write(0x23, 0x6, 1, &val8, 1);
206 i2c_write(0x23, 0x7, 1, &val8, 1);
208 i2c_write(0x23, 0x2, 1, &val8, 1);
209 i2c_write(0x23, 0x3, 1, &val8, 1);
212 i2c_write(0x26, 0x6, 1, &val8, 1);
214 i2c_write(0x26, 0x7, 1, &val8, 1);
216 val8 = 0xf3; /*PMC1, PMC2, PMC3 slot to PCI bus */
217 i2c_write(0x26, 0x2, 1, &val8, 1);
219 i2c_write(0x26, 0x3, 1, &val8, 1);
222 i2c_write(0x27, 0x6, 1, &val8, 1);
223 i2c_write(0x27, 0x7, 1, &val8, 1);
225 i2c_write(0x27, 0x2, 1, &val8, 1);
227 i2c_write(0x27, 0x3, 1, &val8, 1);
231 * Release PCI RST Output signal
237 hose[0].first_busno = 0;
238 hose[0].last_busno = 0xff;
240 /* PCI memory prefetch space */
241 pci_set_region(hose[0].regions + 0,
244 CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
246 /* PCI memory space */
247 pci_set_region(hose[0].regions + 1,
249 CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM);
252 pci_set_region(hose[0].regions + 2,
254 CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
256 /* System memory space */
257 pci_set_region(hose[0].regions + 3,
258 CFG_PCI_SLV_MEM_LOCAL,
260 CFG_PCI_SLV_MEM_SIZE,
261 PCI_REGION_MEM | PCI_REGION_MEMORY);
263 hose[0].region_count = 4;
265 pci_setup_indirect(&hose[0],
266 (CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304));
268 pci_register_hose(hose);
271 * Write command register
274 dev = PCI_BDF(0, 0, 0);
275 pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16);
276 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
277 pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);
280 * Clear non-reserved bits in status register.
282 pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
283 pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
284 pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
286 printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n");
291 hose->last_busno = pci_hose_scan(hose);
293 #endif /* CONFIG_PCISLAVE */
294 #endif /* CONFIG_PCI */