3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
30 * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
31 * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
32 * parameters from the datasheet are:
33 * Tclk = 7.5ns (CL = 2)
39 * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
40 * period is 10ns and the parameters needed for the Timing Register are:
41 * CASL = CL = 2 clock cycles
42 * PTA = Trp = 15ns / 10ns = 2 clock cycles
43 * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
44 * LDF = 2 clock cycles (but can be extended to meet board-level timing)
45 * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
46 * RCD = Trcd = 15ns / 10ns= 2 clock cycles
48 * The actual bit settings in the register would be:
57 * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
58 * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
59 * defined as Trc rather than Trfc.
60 * When using DIMM modules, most but not all of the required timing parameters can be read
61 * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
62 * are not available from the EEPROM
67 #include <asm/processor.h>
68 #include <405gp_i2c.h>
70 #include "../common/common_util.h"
73 extern block_dev_desc_t * scsi_get_dev(int dev);
74 extern block_dev_desc_t * ide_get_dev(int dev);
77 #define ENABLE_ECC /* for ecc boards */
81 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
82 #ifndef __ldiv_t_defined
84 long int quot; /* Quotient */
85 long int rem; /* Remainder */
87 extern ldiv_t ldiv (long int __numer, long int __denom);
88 # define __ldiv_t_defined 1
92 #define PLD_PART_REG PER_PLD_ADDR + 0
93 #define PLD_VERS_REG PER_PLD_ADDR + 1
94 #define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
95 #define PLD_IRQ_REG PER_PLD_ADDR + 3
96 #define PLD_COM_MODE_REG PER_PLD_ADDR + 4
97 #define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
99 #define MEGA_BYTE (1024*1024)
102 unsigned char boardtype; /* Board revision and Population Options */
103 unsigned char cal; /* cas Latency (will be programmend as cal-1) */
104 unsigned char trp; /* datain27 in clocks */
105 unsigned char trcd; /* datain29 in clocks */
106 unsigned char tras; /* datain30 in clocks */
107 unsigned char tctp; /* tras - trcd in clocks */
108 unsigned char am; /* Address Mod (will be programmed as am-1) */
109 unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
110 unsigned char ecc; /* if true, ecc is enabled */
112 #if defined(CONFIG_MIP405T)
113 const sdram_t sdram_table[] = {
114 { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */
115 3, /* Case Latenty = 3 */
116 3, /* trp 20ns / 7.5 ns datain[27] */
117 3, /* trcd 20ns /7.5 ns (datain[29]) */
118 6, /* tras 44ns /7.5 ns (datain[30]) */
119 4, /* tcpt 44 - 20ns = 24ns */
120 2, /* Address Mode = 2 (12x9x4) */
121 3, /* size value (32MByte) */
122 0}, /* ECC disabled */
123 { 0xff, /* terminator */
133 const sdram_t sdram_table[] = {
134 { 0x0f, /* Rev A, 128MByte -1 Board */
135 3, /* Case Latenty = 3 */
136 3, /* trp 20ns / 7.5 ns datain[27] */
137 3, /* trcd 20ns /7.5 ns (datain[29]) */
138 6, /* tras 44ns /7.5 ns (datain[30]) */
139 4, /* tcpt 44 - 20ns = 24ns */
140 3, /* Address Mode = 3 */
142 1}, /* ECC enabled */
143 { 0x07, /* Rev A, 64MByte -2 Board */
144 3, /* Case Latenty = 3 */
145 3, /* trp 20ns / 7.5 ns datain[27] */
146 3, /* trcd 20ns /7.5 ns (datain[29]) */
147 6, /* tras 44ns /7.5 ns (datain[30]) */
148 4, /* tcpt 44 - 20ns = 24ns */
149 2, /* Address Mode = 2 */
151 1}, /* ECC enabled */
152 { 0x03, /* Rev A, 128MByte -4 Board */
153 3, /* Case Latenty = 3 */
154 3, /* trp 20ns / 7.5 ns datain[27] */
155 3, /* trcd 20ns /7.5 ns (datain[29]) */
156 6, /* tras 44ns /7.5 ns (datain[30]) */
157 4, /* tcpt 44 - 20ns = 24ns */
158 3, /* Address Mode = 3 */
160 1}, /* ECC enabled */
161 { 0x1f, /* Rev B, 128MByte -3 Board */
162 3, /* Case Latenty = 3 */
163 3, /* trp 20ns / 7.5 ns datain[27] */
164 3, /* trcd 20ns /7.5 ns (datain[29]) */
165 6, /* tras 44ns /7.5 ns (datain[30]) */
166 4, /* tcpt 44 - 20ns = 24ns */
167 3, /* Address Mode = 3 */
169 1}, /* ECC enabled */
170 { 0xff, /* terminator */
179 #endif /*CONFIG_MIP405T */
180 void SDRAM_err (const char *s)
183 DECLARE_GLOBAL_DATA_PTR;
185 (void) get_clocks ();
191 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
196 unsigned char get_board_revcfg (void)
198 out8 (PER_BOARD_ADDR, 0);
199 return (in8 (PER_BOARD_ADDR));
205 void write_hex (unsigned char i)
212 serial_putc (cc + 55);
214 serial_putc (cc + 48);
217 serial_putc (cc + 55);
219 serial_putc (cc + 48);
222 void write_4hex (unsigned long val)
224 write_hex ((unsigned char) (val >> 24));
225 write_hex ((unsigned char) (val >> 16));
226 write_hex ((unsigned char) (val >> 8));
227 write_hex ((unsigned char) val);
233 int init_sdram (void)
235 DECLARE_GLOBAL_DATA_PTR;
237 unsigned long tmp, baseaddr;
239 unsigned char trp_clocks,
244 unsigned char cal_val;
246 unsigned long sdram_tim, sdram_bank;
248 /*i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);*/
249 (void) get_clocks ();
253 mtdcr (ebccfga, pb7ap);
254 mtdcr (ebccfgd, PLD_AP);
255 mtdcr (ebccfga, pb7cr);
256 mtdcr (ebccfgd, PLD_CR);
257 /* THIS IS OBSOLETE */
258 /* set up the board rev reg*/
259 mtdcr (ebccfga, pb5ap);
260 mtdcr (ebccfgd, BOARD_AP);
261 mtdcr (ebccfga, pb5cr);
262 mtdcr (ebccfgd, BOARD_CR);
264 /* get all informations from PLD */
265 serial_puts ("\nPLD Part 0x");
266 bc = in8 (PLD_PART_REG);
268 serial_puts ("\nPLD Vers 0x");
269 bc = in8 (PLD_VERS_REG);
271 serial_puts ("\nBoard Rev 0x");
272 bc = in8 (PLD_BOARD_CFG_REG);
277 bc = in8 (PLD_PART_REG);
278 #if defined(CONFIG_MIP405T)
280 SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
282 if((bc & 0x80)==0x80)
283 SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
285 /* set-up the chipselect machine */
286 mtdcr (ebccfga, pb0cr); /* get cs0 config reg */
287 tmp = mfdcr (ebccfgd);
288 if ((tmp & 0x00002000) == 0) {
289 /* MPS Boot, set up the flash */
290 mtdcr (ebccfga, pb1ap);
291 mtdcr (ebccfgd, FLASH_AP);
292 mtdcr (ebccfga, pb1cr);
293 mtdcr (ebccfgd, FLASH_CR);
295 /* Flash boot, set up the MPS */
296 mtdcr (ebccfga, pb1ap);
297 mtdcr (ebccfgd, MPS_AP);
298 mtdcr (ebccfga, pb1cr);
299 mtdcr (ebccfgd, MPS_CR);
301 /* set up UART0 (CS2) and UART1 (CS3) */
302 mtdcr (ebccfga, pb2ap);
303 mtdcr (ebccfgd, UART0_AP);
304 mtdcr (ebccfga, pb2cr);
305 mtdcr (ebccfgd, UART0_CR);
306 mtdcr (ebccfga, pb3ap);
307 mtdcr (ebccfgd, UART1_AP);
308 mtdcr (ebccfga, pb3cr);
309 mtdcr (ebccfgd, UART1_CR);
310 bc = in8 (PLD_BOARD_CFG_REG);
312 serial_puts ("\nstart SDRAM Setup\n");
313 serial_puts ("\nBoard Rev: ");
318 baseaddr = CFG_SDRAM_BASE;
319 while (sdram_table[i].sz != 0xff) {
320 if (sdram_table[i].boardtype == bc)
324 if (sdram_table[i].boardtype != bc)
325 SDRAM_err ("No SDRAM table found for this board!!!\n");
327 serial_puts (" found table ");
331 /* since the ECC initialisation needs some time,
332 * we show that we're alive
334 if (sdram_table[i].ecc)
335 serial_puts ("\nInitializing SDRAM, Please stand by");
336 cal_val = sdram_table[i].cal - 1; /* Cas Latency */
337 trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */
338 trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
339 tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
340 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
341 tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */
342 /* trc_clocks is sum of trp_clocks + tras_clocks */
343 trc_clocks = trp_clocks + tras_clocks;
344 /* get SDRAM timing register */
345 mtdcr (memcfga, mem_sdtr1);
346 sdram_tim = mfdcr (memcfgd) & ~0x018FC01F;
347 /* insert CASL value */
348 sdram_tim |= ((unsigned long) (cal_val)) << 23;
349 /* insert PTA value */
350 sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
351 /* insert CTP value */
353 ((unsigned long) (trc_clocks - trp_clocks -
355 /* insert LDF (always 01) */
356 sdram_tim |= ((unsigned long) 0x01) << 14;
357 /* insert RFTA value */
358 sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
359 /* insert RCD value */
360 sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
362 tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */
363 /* insert SZ value; */
364 tmp |= ((unsigned long) sdram_table[i].sz << 17);
365 /* get SDRAM bank 0 register */
366 mtdcr (memcfga, mem_mb0cf);
367 sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001;
368 sdram_bank |= (baseaddr | tmp | 0x01);
371 serial_puts ("sdtr: ");
372 write_4hex (sdram_tim);
376 /* write SDRAM timing register */
377 mtdcr (memcfga, mem_sdtr1);
378 mtdcr (memcfgd, sdram_tim);
381 serial_puts ("mb0cf: ");
382 write_4hex (sdram_bank);
386 /* write SDRAM bank 0 register */
387 mtdcr (memcfga, mem_mb0cf);
388 mtdcr (memcfgd, sdram_bank);
390 if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
391 /* get SDRAM refresh interval register */
392 mtdcr (memcfga, mem_rtr);
393 tmp = mfdcr (memcfgd) & ~0x3FF80000;
396 /* get SDRAM refresh interval register */
397 mtdcr (memcfga, mem_rtr);
398 tmp = mfdcr (memcfgd) & ~0x3FF80000;
401 /* write SDRAM refresh interval register */
402 mtdcr (memcfga, mem_rtr);
403 mtdcr (memcfgd, tmp);
404 /* enable ECC if used */
405 #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
406 if (sdram_table[i].ecc) {
407 /* disable checking for all banks */
410 serial_puts ("disable ECC.. ");
412 mtdcr (memcfga, mem_ecccf);
413 tmp = mfdcr (memcfgd);
414 tmp &= 0xff0fffff; /* disable all banks */
415 mtdcr (memcfga, mem_ecccf);
416 /* set up SDRAM Controller with ECC enabled */
418 serial_puts ("setup SDRAM Controller.. ");
420 mtdcr (memcfgd, tmp);
421 mtdcr (memcfga, mem_mcopt1);
422 tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
423 mtdcr (memcfga, mem_mcopt1);
424 mtdcr (memcfgd, tmp);
427 serial_puts ("fill the memory..\n");
430 /* now, fill all the memory */
431 tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
432 p = (unsigned long) 0;
433 while ((unsigned long) p < tmp) {
435 if (!((unsigned long) p % 0x00800000)) /* every 8MByte */
441 serial_puts ("enable ECC\n");
444 mtdcr (memcfga, mem_ecccf);
445 tmp = mfdcr (memcfgd);
446 tmp |= 0x00800000; /* enable bank 0 */
447 mtdcr (memcfgd, tmp);
452 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
453 mtdcr (memcfga, mem_mcopt1);
454 tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000;
455 mtdcr (memcfga, mem_mcopt1);
456 mtdcr (memcfgd, tmp);
463 int board_pre_init (void)
467 /*-------------------------------------------------------------------------+
468 | Interrupt controller setup for the PIP405 board.
469 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
470 | IRQ 16 405GP internally generated; active low; level sensitive
472 | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
473 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
474 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
475 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
476 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
477 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
478 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
479 | Note for MIP405 board:
480 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
481 | the Interrupt Controller in the South Bridge has caused the
482 | interrupt. The IC must be read to determine which device
483 | caused the interrupt.
485 +-------------------------------------------------------------------------*/
486 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
487 mtdcr (uicer, 0x00000000); /* disable all ints */
488 mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
489 mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
490 mtdcr (uictr, 0x10000000); /* set int trigger levels */
491 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
492 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
498 * Get some PLD Registers
501 unsigned short get_pld_parvers (void)
503 unsigned short result;
506 rc = in8 (PLD_PART_REG);
507 result = (unsigned short) rc << 8;
508 rc = in8 (PLD_VERS_REG);
514 void user_led0 (unsigned char on)
517 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
519 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
523 void ide_set_reset (int idereset)
525 /* if reset = 1 IDE reset will be asserted */
527 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
530 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
535 /* ------------------------------------------------------------------------- */
537 void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
539 #if !defined(CONFIG_MIP405T)
540 unsigned char bc,rc,tmp;
543 bc = in8 (PLD_BOARD_CFG_REG);
547 for (i = 0; i < 4; i++) {
553 if((((bc>>4) & 0xf)==0x1) /* Rev B PCB with */
554 && (rc==0x1)) /* Population Option 1 is a -3 */
556 *pcbrev=(bc >> 4) & 0xf;
560 bc = in8 (PLD_BOARD_CFG_REG);
561 *pcbrev=(bc >> 4) & 0xf;
567 * Check Board Identity:
569 /* serial String: "MIP405_1000" OR "MIP405T_1000" */
570 #if !defined(CONFIG_MIP405T)
571 #define BOARD_NAME "MIP405"
573 #define BOARD_NAME "MIP405T"
576 int checkboard (void)
579 unsigned char bc, var;
581 backup_t *b = (backup_t *) s;
584 get_pcbrev_var(&bc,&var);
585 i = getenv_r ("serial#", s, 32);
586 if ((i == 0) || strncmp (s, BOARD_NAME,sizeof(BOARD_NAME))) {
587 get_backup_values (b);
588 if (strncmp (b->signature, "MPL\0", 4) != 0) {
589 puts ("### No HW ID - assuming " BOARD_NAME);
590 printf ("-%d Rev %c", var, 'A' + bc);
592 b->serial_name[sizeof(BOARD_NAME)-1] = 0;
593 printf ("%s-%d Rev %c SN: %s", b->serial_name, var,
594 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]);
597 s[sizeof(BOARD_NAME)-1] = 0;
598 printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc,
599 &s[sizeof(BOARD_NAME)]);
601 bc = in8 (PLD_EXT_CONF_REG);
602 printf (" Boot Config: 0x%x\n", bc);
607 /* ------------------------------------------------------------------------- */
608 /* ------------------------------------------------------------------------- */
610 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
611 the necessary info for SDRAM controller configuration
613 /* ------------------------------------------------------------------------- */
614 /* ------------------------------------------------------------------------- */
615 static int test_dram (unsigned long ramsize);
617 long int initdram (int board_type)
620 unsigned long bank_reg[4], tmp, bank_size;
622 unsigned long TotalSize;
625 /* since the DRAM controller is allready set up, calculate the size with the
627 mtdcr (memcfga, mem_mb0cf);
628 bank_reg[0] = mfdcr (memcfgd);
629 mtdcr (memcfga, mem_mb1cf);
630 bank_reg[1] = mfdcr (memcfgd);
631 mtdcr (memcfga, mem_mb2cf);
632 bank_reg[2] = mfdcr (memcfgd);
633 mtdcr (memcfga, mem_mb3cf);
634 bank_reg[3] = mfdcr (memcfgd);
636 for (i = 0; i < 4; i++) {
637 if ((bank_reg[i] & 0x1) == 0x1) {
638 tmp = (bank_reg[i] >> 17) & 0x7;
639 bank_size = 4 << tmp;
640 TotalSize += bank_size;
644 mtdcr (memcfga, mem_ecccf);
645 tmp = mfdcr (memcfgd);
651 test_dram (TotalSize * MEGA_BYTE);
652 return (TotalSize * MEGA_BYTE);
655 /* ------------------------------------------------------------------------- */
658 static int test_dram (unsigned long ramsize)
661 mem_test (0L, ramsize, 1);
663 /* not yet implemented */
667 /* used to check if the time in RTC is valid */
668 static unsigned long start;
669 static struct rtc_time tm;
671 int misc_init_r (void)
673 /* check, if RTC is running */
676 /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
677 if (mfdcr(strap) & PSR_ROM_LOC)
678 mtspr(ccr0, (mfspr(ccr0) & ~0x80));
684 void print_mip405_rev (void)
686 unsigned char part, vers, pcbrev, var;
688 get_pcbrev_var(&pcbrev,&var);
689 part = in8 (PLD_PART_REG);
690 vers = in8 (PLD_VERS_REG);
691 printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n",
692 var, pcbrev + 'A', part & 0x7F, vers);
695 extern void mem_test_reloc(void);
696 extern int mk_date (char *, struct rtc_time *);
698 int last_stage_init (void)
701 struct rtc_time newtm;
704 /* write correct LED configuration */
705 if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
706 printf ("Error writing to the PHY\n");
708 /* since LED/CFG2 is not connected on the -2,
709 * write to correct capability information */
710 if (miiphy_write (0x1, 0x4, 0x01E1) != 0) {
711 printf ("Error writing to the PHY\n");
716 /* check if RTC time is valid */
717 stop=get_timer(start);
718 while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */
720 stop=get_timer(start);
723 if(tm.tm_sec==newtm.tm_sec) {
724 s=getenv("defaultdate");
726 mk_date ("010112001970", &newtm);
728 if(mk_date (s, &newtm)!=0) {
729 printf("RTC: Bad date format in defaultdate\n");
738 /***************************************************************************
739 * some helping routines
742 int overwrite_console (void)
744 return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */
748 /************************************************************************
750 ************************************************************************/
751 void print_mip405_info (void)
753 unsigned char part, vers, cfg, irq_reg, com_mode, ext;
755 part = in8 (PLD_PART_REG);
756 vers = in8 (PLD_VERS_REG);
757 cfg = in8 (PLD_BOARD_CFG_REG);
758 irq_reg = in8 (PLD_IRQ_REG);
759 com_mode = in8 (PLD_COM_MODE_REG);
760 ext = in8 (PLD_EXT_CONF_REG);
762 printf ("PLD Part %d version %d\n", part & 0x7F, vers);
763 printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
764 printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
765 (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
766 printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
767 printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
768 #if !defined(CONFIG_MIP405T)
769 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
770 (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
771 (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
772 (ext >> 6) & 0x1, (ext >> 7) & 0x1);
773 printf ("SER1 uses handshakes %s\n",
774 (ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
776 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
777 (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
778 (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
779 (ext >> 6) & 0x1,(ext >> 7) & 0x1);
781 printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
783 printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
784 #if !defined(CONFIG_MIP405T)
785 printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
786 printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
788 printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active");
789 printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
790 printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active");