3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
31 #include "../common/isa.h"
32 #include "../common/common_util.h"
39 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
40 #ifndef __ldiv_t_defined
42 long int quot; /* Quotient */
43 long int rem; /* Remainder */
45 extern ldiv_t ldiv (long int __numer, long int __denom);
47 # define __ldiv_t_defined 1
55 SDRAM_UNSUPPORTED_ERR,
60 const unsigned char mode;
61 const unsigned char row;
62 const unsigned char col;
63 const unsigned char bank;
66 static const SDRAM_SETUP sdram_setup_table[] = {
85 static const unsigned char cal_indextable[] = {
91 * translate ns.ns/10 coding of SPD timing values
92 * into 10 ps unit values
95 unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version)
97 unsigned short ns, ns10;
99 /* isolate upper nibble */
100 ns = (spd_byte >> 4) & 0x0F;
101 /* isolate lower nibble */
102 ns10 = (spd_byte & 0x0F);
104 return (ns * 100 + ns10 * 10);
108 * translate ns.ns/4 coding of SPD timing values
109 * into 10 ps unit values
112 unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version)
114 unsigned short ns, ns4;
116 /* isolate upper 6 bits */
117 ns = (spd_byte >> 2) & 0x3F;
118 /* isloate lower 2 bits */
119 ns4 = (spd_byte & 0x03);
121 return (ns * 100 + ns4 * 25);
125 * translate ns coding of SPD timing values
126 * into 10 ps unit values
129 unsigned short NSto10PS (unsigned char spd_byte)
131 return (spd_byte * 100);
134 void SDRAM_err (const char *s)
137 DECLARE_GLOBAL_DATA_PTR;
139 (void) get_clocks ();
145 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
152 void write_hex (unsigned char i)
159 serial_putc (cc + 55);
161 serial_putc (cc + 48);
164 serial_putc (cc + 55);
166 serial_putc (cc + 48);
169 void write_4hex (unsigned long val)
171 write_hex ((unsigned char) (val >> 24));
172 write_hex ((unsigned char) (val >> 16));
173 write_hex ((unsigned char) (val >> 8));
174 write_hex ((unsigned char) val);
179 int board_pre_init (void)
181 unsigned char dataout[1];
182 unsigned char datain[128];
183 unsigned long sdram_size;
184 SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
185 unsigned long memclk;
186 unsigned long tmemclk = 0;
187 unsigned long tmp, bank, baseaddr, bank_size;
189 unsigned char rows, cols, banks, sdram_banks, density;
190 unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
191 trc_clocks, tctp_clocks;
192 unsigned char cal_index, cal_val, spd_version, spd_chksum;
193 unsigned char buf[8];
195 DECLARE_GLOBAL_DATA_PTR;
198 memclk = get_bus_freq (tmemclk);
199 tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
202 (void) get_clocks ();
205 serial_puts ("\nstart SDRAM Setup\n");
208 /* Read Serial Presence Detect Information */
209 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
211 for (i = 0; i < 128; i++)
213 i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
215 serial_puts ("\ni2c_read returns ");
221 for (i = 0; i < 128; i++) {
222 write_hex (datain[i]);
224 if (((i + 1) % 16) == 0)
230 for (i = 0; i < 63; i++) {
231 spd_chksum += datain[i];
233 if (datain[63] != spd_chksum) {
235 serial_puts ("SPD chksum: 0x");
236 write_hex (datain[63]);
237 serial_puts (" != calc. chksum: 0x");
238 write_hex (spd_chksum);
241 SDRAM_err ("SPD checksum Error");
243 /* SPD seems to be ok, use it */
245 /* get SPD version */
246 spd_version = datain[62];
248 /* do some sanity checks on the kind of RAM */
249 if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */
250 (datain[2] != 0x04) || /* if not SDRAM */
251 (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */
252 (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */
253 (datain[126] == 0x66)) /* or a 66Mhz modules */
254 SDRAM_err ("unsupported SDRAM");
256 serial_puts ("SDRAM sanity ok\n");
259 /* get number of rows/cols/banks out of byte 3+4+5 */
264 /* get number of SDRAM banks out of byte 17 and
265 supported CAS latencies out of byte 18 */
266 sdram_banks = datain[17];
267 supported_cal = datain[18] & ~0x81;
269 while (t->mode != 0) {
270 if ((t->row == rows) && (t->col == cols)
271 && (t->bank == sdram_banks))
277 serial_puts ("rows: ");
279 serial_puts (" cols: ");
281 serial_puts (" banks: ");
283 serial_puts (" mode: ");
288 SDRAM_err ("unsupported SDRAM");
289 /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
291 serial_puts ("tRP: ");
292 write_hex (datain[27]);
293 serial_puts ("\ntRCD: ");
294 write_hex (datain[29]);
295 serial_puts ("\ntRAS: ");
296 write_hex (datain[30]);
300 trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk;
301 trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk;
302 tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk;
303 density = datain[31];
305 /* trc_clocks is sum of trp_clocks + tras_clocks */
306 trc_clocks = trp_clocks + tras_clocks;
307 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
309 ((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
310 (tmemclk - 1)) / tmemclk;
313 serial_puts ("c_RP: ");
314 write_hex (trp_clocks);
315 serial_puts ("\nc_RCD: ");
316 write_hex (trcd_clocks);
317 serial_puts ("\nc_RAS: ");
318 write_hex (tras_clocks);
319 serial_puts ("\nc_RC: (RP+RAS): ");
320 write_hex (trc_clocks);
321 serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
322 write_hex (tctp_clocks);
323 serial_puts ("\nt_CTP: RAS - RCD: ");
325 char) ((NSto10PS (datain[30]) -
326 NSto10PS (datain[29])) >> 8));
327 write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29])));
328 serial_puts ("\ntmemclk: ");
329 write_hex ((unsigned char) (tmemclk >> 8));
330 write_hex ((unsigned char) (tmemclk));
336 for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) {
337 /* is this CAS latency supported ? */
338 if ((supported_cal >> i) & 0x01) {
339 buf[0] = datain[cal_indextable[cal_index]];
341 if (NS10to10PS (buf[0], spd_version) <= tmemclk)
344 /* SPD bytes 25+26 have another format */
345 if (NS4to10PS (buf[0], spd_version) <= tmemclk)
352 serial_puts ("CAL: ");
353 write_hex (cal_val + 1);
358 SDRAM_err ("unsupported SDRAM");
360 /* get SDRAM timing register */
361 mtdcr (memcfga, mem_sdtr1);
362 tmp = mfdcr (memcfgd) & ~0x018FC01F;
363 /* insert CASL value */
364 /* tmp |= ((unsigned long)cal_val) << 23; */
365 tmp |= ((unsigned long) cal_val) << 23;
366 /* insert PTA value */
367 tmp |= ((unsigned long) (trp_clocks - 1)) << 18;
368 /* insert CTP value */
369 /* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
370 tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16;
371 /* insert LDF (always 01) */
372 tmp |= ((unsigned long) 0x01) << 14;
373 /* insert RFTA value */
374 tmp |= ((unsigned long) (trc_clocks - 4)) << 2;
375 /* insert RCD value */
376 tmp |= ((unsigned long) (trcd_clocks - 1)) << 0;
379 serial_puts ("sdtr: ");
384 /* write SDRAM timing register */
385 mtdcr (memcfga, mem_sdtr1);
386 mtdcr (memcfgd, tmp);
387 baseaddr = CFG_SDRAM_BASE;
388 bank_size = (((unsigned long) density) << 22) / 2;
389 /* insert AM value */
390 tmp = ((unsigned long) t->mode - 1) << 13;
391 /* insert SZ value; */
394 tmp |= ((unsigned long) 0x00) << 17;
397 tmp |= ((unsigned long) 0x01) << 17;
400 tmp |= ((unsigned long) 0x02) << 17;
403 tmp |= ((unsigned long) 0x03) << 17;
406 tmp |= ((unsigned long) 0x04) << 17;
409 tmp |= ((unsigned long) 0x05) << 17;
412 tmp |= ((unsigned long) 0x06) << 17;
415 SDRAM_err ("unsupported SDRAM");
417 /* get SDRAM bank 0 register */
418 mtdcr (memcfga, mem_mb0cf);
419 bank = mfdcr (memcfgd) & ~0xFFCEE001;
420 bank |= (baseaddr | tmp | 0x01);
422 serial_puts ("bank0: baseaddr: ");
423 write_4hex (baseaddr);
424 serial_puts (" banksize: ");
425 write_4hex (bank_size);
426 serial_puts (" mb0cf: ");
430 baseaddr += bank_size;
431 sdram_size += bank_size;
433 /* write SDRAM bank 0 register */
434 mtdcr (memcfga, mem_mb0cf);
435 mtdcr (memcfgd, bank);
437 /* get SDRAM bank 1 register */
438 mtdcr (memcfga, mem_mb1cf);
439 bank = mfdcr (memcfgd) & ~0xFFCEE001;
443 serial_puts ("bank1: baseaddr: ");
444 write_4hex (baseaddr);
445 serial_puts (" banksize: ");
446 write_4hex (bank_size);
449 bank |= (baseaddr | tmp | 0x01);
450 baseaddr += bank_size;
451 sdram_size += bank_size;
454 serial_puts (" mb1cf: ");
458 /* write SDRAM bank 1 register */
459 mtdcr (memcfga, mem_mb1cf);
460 mtdcr (memcfgd, bank);
462 /* get SDRAM bank 2 register */
463 mtdcr (memcfga, mem_mb2cf);
464 bank = mfdcr (memcfgd) & ~0xFFCEE001;
466 bank |= (baseaddr | tmp | 0x01);
469 serial_puts ("bank2: baseaddr: ");
470 write_4hex (baseaddr);
471 serial_puts (" banksize: ");
472 write_4hex (bank_size);
473 serial_puts (" mb2cf: ");
478 baseaddr += bank_size;
479 sdram_size += bank_size;
481 /* write SDRAM bank 2 register */
482 mtdcr (memcfga, mem_mb2cf);
483 mtdcr (memcfgd, bank);
485 /* get SDRAM bank 3 register */
486 mtdcr (memcfga, mem_mb3cf);
487 bank = mfdcr (memcfgd) & ~0xFFCEE001;
490 serial_puts ("bank3: baseaddr: ");
491 write_4hex (baseaddr);
492 serial_puts (" banksize: ");
493 write_4hex (bank_size);
497 bank |= (baseaddr | tmp | 0x01);
498 baseaddr += bank_size;
499 sdram_size += bank_size;
503 serial_puts (" mb3cf: ");
508 /* write SDRAM bank 3 register */
509 mtdcr (memcfga, mem_mb3cf);
510 mtdcr (memcfgd, bank);
513 /* get SDRAM refresh interval register */
514 mtdcr (memcfga, mem_rtr);
515 tmp = mfdcr (memcfgd) & ~0x3FF80000;
517 if (tmemclk < NSto10PS (16))
522 /* write SDRAM refresh interval register */
523 mtdcr (memcfga, mem_rtr);
524 mtdcr (memcfgd, tmp);
526 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
527 mtdcr (memcfga, mem_mcopt1);
528 tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80E00000;
529 mtdcr (memcfga, mem_mcopt1);
530 mtdcr (memcfgd, tmp);
533 /*-------------------------------------------------------------------------+
534 | Interrupt controller setup for the PIP405 board.
535 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
536 | IRQ 16 405GP internally generated; active low; level sensitive
538 | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
539 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
540 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
541 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
542 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
543 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
544 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
545 | Note for PIP405 board:
546 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
547 | the Interrupt Controller in the South Bridge has caused the
548 | interrupt. The IC must be read to determine which device
549 | caused the interrupt.
551 +-------------------------------------------------------------------------*/
552 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
553 mtdcr (uicer, 0x00000000); /* disable all ints */
554 mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
555 mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
556 mtdcr (uictr, 0x10000000); /* set int trigger levels */
557 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
558 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
564 /* ------------------------------------------------------------------------- */
567 * Check Board Identity:
570 int checkboard (void)
575 backup_t *b = (backup_t *) s;
579 i = getenv_r ("serial#", s, 32);
580 if ((i == 0) || strncmp (s, "PIP405", 6)) {
581 get_backup_values (b);
582 if (strncmp (b->signature, "MPL\0", 4) != 0) {
583 puts ("### No HW ID - assuming PIP405");
585 b->serial_name[6] = 0;
586 printf ("%s SN: %s", b->serial_name,
591 printf ("%s SN: %s", s, &s[7]);
593 bc = in8 (CONFIG_PORT_ADDR);
594 printf (" Boot Config: 0x%x\n", bc);
599 /* ------------------------------------------------------------------------- */
600 /* ------------------------------------------------------------------------- */
602 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
603 the necessary info for SDRAM controller configuration
605 /* ------------------------------------------------------------------------- */
606 /* ------------------------------------------------------------------------- */
607 static int test_dram (unsigned long ramsize);
609 long int initdram (int board_type)
611 DECLARE_GLOBAL_DATA_PTR;
613 unsigned long bank_reg[4], tmp, bank_size;
615 unsigned long TotalSize;
618 /* since the DRAM controller is allready set up,
619 * calculate the size with the bank registers
621 mtdcr (memcfga, mem_mb0cf);
622 bank_reg[0] = mfdcr (memcfgd);
623 mtdcr (memcfga, mem_mb1cf);
624 bank_reg[1] = mfdcr (memcfgd);
625 mtdcr (memcfga, mem_mb2cf);
626 bank_reg[2] = mfdcr (memcfgd);
627 mtdcr (memcfga, mem_mb3cf);
628 bank_reg[3] = mfdcr (memcfgd);
630 for (i = 0; i < 4; i++) {
631 if ((bank_reg[i] & 0x1) == 0x1) {
632 tmp = (bank_reg[i] >> 17) & 0x7;
633 bank_size = 4 << tmp;
634 TotalSize += bank_size;
639 printf ("single-sided DIMM ");
641 printf ("double-sided DIMM ");
642 test_dram (TotalSize * 1024 * 1024);
643 /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
645 if (gd->cpu_clk > 220000000)
647 return (TotalSize * 1024 * 1024);
650 /* ------------------------------------------------------------------------- */
653 static int test_dram (unsigned long ramsize)
655 /* not yet implemented */
660 int misc_init_r (void)
665 /***************************************************************************
666 * some helping routines
669 int overwrite_console (void)
671 return (in8 (CONFIG_PORT_ADDR) & 0x1); /* return TRUE if console should be overwritten */
675 extern int isa_init (void);
678 void print_pip405_rev (void)
680 unsigned char part, vers, cfg;
682 part = in8 (PLD_PART_REG);
683 vers = in8 (PLD_VERS_REG);
684 cfg = in8 (PLD_BOARD_CFG_REG);
685 printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
686 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf,
687 vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf);
690 extern void check_env(void);
693 int last_stage_init (void)
702 /************************************************************************
704 ************************************************************************/
705 void print_pip405_info (void)
707 unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr,
708 compwr, nicvga, scsirst;
710 part = in8 (PLD_PART_REG);
711 vers = in8 (PLD_VERS_REG);
712 cfg = in8 (PLD_BOARD_CFG_REG);
713 ledu = in8 (PLD_LED_USER_REG);
714 sysman = in8 (PLD_SYS_MAN_REG);
715 flashcom = in8 (PLD_FLASH_COM_REG);
716 can = in8 (PLD_CAN_REG);
717 serpwr = in8 (PLD_SER_PWR_REG);
718 compwr = in8 (PLD_COM_PWR_REG);
719 nicvga = in8 (PLD_NIC_VGA_REG);
720 scsirst = in8 (PLD_SCSI_RST_REG);
721 printf ("PLD Part %d version %d\n",
722 part & 0xf, vers & 0xf);
723 printf ("PLD Part %d version %d\n",
724 (part >> 4) & 0xf, (vers >> 4) & 0xf);
725 printf ("Board Revision %c\n", (cfg & 0xf) + 'A');
726 printf ("Population Options %d %d %d %d\n",
727 (cfg >> 4) & 0x1, (cfg >> 5) & 0x1,
728 (cfg >> 6) & 0x1, (cfg >> 7) & 0x1);
729 printf ("User LED0 %s User LED1 %s\n",
730 ((ledu & 0x1) == 0x1) ? "on" : "off",
731 ((ledu & 0x2) == 0x2) ? "on" : "off");
732 printf ("Additionally Options %d %d\n",
733 (ledu >> 2) & 0x1, (ledu >> 3) & 0x1);
734 printf ("User Config Switch %d %d %d %d\n",
735 (ledu >> 4) & 0x1, (ledu >> 5) & 0x1,
736 (ledu >> 6) & 0x1, (ledu >> 7) & 0x1);
737 switch (sysman & 0x3) {
739 printf ("PCI Clocks are running\n");
742 printf ("PCI Clocks are stopped in POS State\n");
745 printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
748 printf ("PCI Clocks are stopped\n");
751 switch ((sysman >> 2) & 0x3) {
753 printf ("Main Clocks are running\n");
756 printf ("Main Clocks are stopped in POS State\n");
760 printf ("PCI Clocks are stopped\n");
763 printf ("INIT asserts %sINT2# (SMI)\n",
764 ((sysman & 0x10) == 0x10) ? "" : "not ");
765 printf ("INIT asserts %sINT1# (NMI)\n",
766 ((sysman & 0x20) == 0x20) ? "" : "not ");
767 printf ("INIT occured %d\n", (sysman >> 6) & 0x1);
768 printf ("SER1 is routed to %s\n",
769 ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
770 printf ("COM2 is routed to %s\n",
771 ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232");
772 printf ("RS485 is configured as %s duplex\n",
773 ((flashcom & 0x4) == 0x4) ? "full" : "half");
774 printf ("RS485 is connected to %s\n",
775 ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2");
776 printf ("SER1 uses handshakes %s\n",
777 ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
778 printf ("Bootflash is %swriteprotected\n",
779 ((flashcom & 0x20) == 0x20) ? "not " : "");
780 printf ("Bootflash VPP is %s\n",
781 ((flashcom & 0x40) == 0x40) ? "on" : "off");
782 printf ("Bootsector is %swriteprotected\n",
783 ((flashcom & 0x80) == 0x80) ? "not " : "");
784 switch ((can) & 0x3) {
786 printf ("CAN Controller is on address 0x1000..0x10FF\n");
789 printf ("CAN Controller is on address 0x8000..0x80FF\n");
792 printf ("CAN Controller is on address 0xE000..0xE0FF\n");
795 printf ("CAN Controller is disabled\n");
798 switch ((can >> 2) & 0x3) {
800 printf ("CAN Controller Reset is ISA Reset\n");
803 printf ("CAN Controller Reset is ISA Reset and POS State\n");
807 printf ("CAN Controller is in reset\n");
810 if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13))
811 printf ("CAN Interrupt is disabled\n");
813 printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf);
814 switch (serpwr & 0x3) {
816 printf ("SER0 Drivers are enabled\n");
819 printf ("SER0 Drivers are disabled in the POS state\n");
823 printf ("SER0 Drivers are disabled\n");
826 switch ((serpwr >> 2) & 0x3) {
828 printf ("SER1 Drivers are enabled\n");
831 printf ("SER1 Drivers are disabled in the POS state\n");
835 printf ("SER1 Drivers are disabled\n");
838 switch (compwr & 0x3) {
840 printf ("COM1 Drivers are enabled\n");
843 printf ("COM1 Drivers are disabled in the POS state\n");
847 printf ("COM1 Drivers are disabled\n");
850 switch ((compwr >> 2) & 0x3) {
852 printf ("COM2 Drivers are enabled\n");
855 printf ("COM2 Drivers are disabled in the POS state\n");
859 printf ("COM2 Drivers are disabled\n");
862 switch ((nicvga) & 0x3) {
864 printf ("PHY is running\n");
867 printf ("PHY is in Power save mode in POS state\n");
871 printf ("PHY is in Power save mode\n");
874 switch ((nicvga >> 2) & 0x3) {
876 printf ("VGA is running\n");
879 printf ("VGA is in Power save mode in POS state\n");
883 printf ("VGA is in Power save mode\n");
886 printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not ");
887 printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not ");
888 printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1,
889 (nicvga >> 7) & 0x1);
890 switch ((scsirst) & 0x3) {
892 printf ("SCSI Controller is running\n");
895 printf ("SCSI Controller is in Power save mode in POS state\n");
899 printf ("SCSI Controller is in Power save mode\n");
902 printf ("SCSI termination is %s\n",
903 ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled");
904 printf ("SCSI Controller is %sreseted\n",
905 ((scsirst & 0x10) == 0x10) ? "" : "not ");
906 printf ("IDE disks are %sreseted\n",
907 ((scsirst & 0x20) == 0x20) ? "" : "not ");
908 printf ("ISA Bus is %sreseted\n",
909 ((scsirst & 0x40) == 0x40) ? "" : "not ");
910 printf ("Super IO is %sreseted\n",
911 ((scsirst & 0x80) == 0x80) ? "" : "not ");
914 void user_led0 (unsigned char on)
917 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
919 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
922 void user_led1 (unsigned char on)
925 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
927 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
930 void ide_set_reset (int idereset)
932 /* if reset = 1 IDE reset will be asserted */
933 unsigned char resreg;
935 resreg = in8 (PLD_SCSI_RST_REG);
942 out8 (PLD_SCSI_RST_REG, resreg);