3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
31 #include "../common/isa.h"
32 #include "../common/common_util.h"
39 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
40 #ifndef __ldiv_t_defined
42 long int quot; /* Quotient */
43 long int rem; /* Remainder */
45 extern ldiv_t ldiv (long int __numer, long int __denom);
47 # define __ldiv_t_defined 1
55 SDRAM_UNSUPPORTED_ERR,
60 const unsigned char mode;
61 const unsigned char row;
62 const unsigned char col;
63 const unsigned char bank;
66 static const SDRAM_SETUP sdram_setup_table[] = {
85 static const unsigned char cal_indextable[] = {
91 * translate ns.ns/10 coding of SPD timing values
92 * into 10 ps unit values
95 unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version)
97 unsigned short ns, ns10;
99 /* isolate upper nibble */
100 ns = (spd_byte >> 4) & 0x0F;
101 /* isolate lower nibble */
102 ns10 = (spd_byte & 0x0F);
104 return (ns * 100 + ns10 * 10);
108 * translate ns.ns/4 coding of SPD timing values
109 * into 10 ps unit values
112 unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version)
114 unsigned short ns, ns4;
116 /* isolate upper 6 bits */
117 ns = (spd_byte >> 2) & 0x3F;
118 /* isloate lower 2 bits */
119 ns4 = (spd_byte & 0x03);
121 return (ns * 100 + ns4 * 25);
125 * translate ns coding of SPD timing values
126 * into 10 ps unit values
129 unsigned short NSto10PS (unsigned char spd_byte)
131 return (spd_byte * 100);
134 void SDRAM_err (const char *s)
137 DECLARE_GLOBAL_DATA_PTR;
139 (void) get_clocks ();
145 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
152 void write_hex (unsigned char i)
159 serial_putc (cc + 55);
161 serial_putc (cc + 48);
164 serial_putc (cc + 55);
166 serial_putc (cc + 48);
169 void write_4hex (unsigned long val)
171 write_hex ((unsigned char) (val >> 24));
172 write_hex ((unsigned char) (val >> 16));
173 write_hex ((unsigned char) (val >> 8));
174 write_hex ((unsigned char) val);
179 int board_pre_init (void)
181 unsigned char dataout[1];
182 unsigned char datain[128];
183 unsigned long sdram_size;
184 SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
185 unsigned long memclk;
186 unsigned long tmemclk = 0;
187 unsigned long tmp, bank, baseaddr, bank_size;
189 unsigned char rows, cols, banks, sdram_banks, density;
190 unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
191 trc_clocks, tctp_clocks;
192 unsigned char cal_index, cal_val, spd_version, spd_chksum;
193 unsigned char buf[8];
195 DECLARE_GLOBAL_DATA_PTR;
197 /* set up the config port */
198 mtdcr (ebccfga, pb7ap);
199 mtdcr (ebccfgd, CONFIG_PORT_AP);
200 mtdcr (ebccfga, pb7cr);
201 mtdcr (ebccfgd, CONFIG_PORT_CR);
203 memclk = get_bus_freq (tmemclk);
204 tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
207 (void) get_clocks ();
210 serial_puts ("\nstart SDRAM Setup\n");
213 /* Read Serial Presence Detect Information */
214 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
216 for (i = 0; i < 128; i++)
218 i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
220 serial_puts ("\ni2c_read returns ");
226 for (i = 0; i < 128; i++) {
227 write_hex (datain[i]);
229 if (((i + 1) % 16) == 0)
235 for (i = 0; i < 63; i++) {
236 spd_chksum += datain[i];
238 if (datain[63] != spd_chksum) {
240 serial_puts ("SPD chksum: 0x");
241 write_hex (datain[63]);
242 serial_puts (" != calc. chksum: 0x");
243 write_hex (spd_chksum);
246 SDRAM_err ("SPD checksum Error");
248 /* SPD seems to be ok, use it */
250 /* get SPD version */
251 spd_version = datain[62];
253 /* do some sanity checks on the kind of RAM */
254 if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */
255 (datain[2] != 0x04) || /* if not SDRAM */
256 (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */
257 (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */
258 (datain[126] == 0x66)) /* or a 66Mhz modules */
259 SDRAM_err ("unsupported SDRAM");
261 serial_puts ("SDRAM sanity ok\n");
264 /* get number of rows/cols/banks out of byte 3+4+5 */
269 /* get number of SDRAM banks out of byte 17 and
270 supported CAS latencies out of byte 18 */
271 sdram_banks = datain[17];
272 supported_cal = datain[18] & ~0x81;
274 while (t->mode != 0) {
275 if ((t->row == rows) && (t->col == cols)
276 && (t->bank == sdram_banks))
282 serial_puts ("rows: ");
284 serial_puts (" cols: ");
286 serial_puts (" banks: ");
288 serial_puts (" mode: ");
293 SDRAM_err ("unsupported SDRAM");
294 /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
296 serial_puts ("tRP: ");
297 write_hex (datain[27]);
298 serial_puts ("\ntRCD: ");
299 write_hex (datain[29]);
300 serial_puts ("\ntRAS: ");
301 write_hex (datain[30]);
305 trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk;
306 trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk;
307 tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk;
308 density = datain[31];
310 /* trc_clocks is sum of trp_clocks + tras_clocks */
311 trc_clocks = trp_clocks + tras_clocks;
312 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
314 ((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
315 (tmemclk - 1)) / tmemclk;
318 serial_puts ("c_RP: ");
319 write_hex (trp_clocks);
320 serial_puts ("\nc_RCD: ");
321 write_hex (trcd_clocks);
322 serial_puts ("\nc_RAS: ");
323 write_hex (tras_clocks);
324 serial_puts ("\nc_RC: (RP+RAS): ");
325 write_hex (trc_clocks);
326 serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
327 write_hex (tctp_clocks);
328 serial_puts ("\nt_CTP: RAS - RCD: ");
330 char) ((NSto10PS (datain[30]) -
331 NSto10PS (datain[29])) >> 8));
332 write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29])));
333 serial_puts ("\ntmemclk: ");
334 write_hex ((unsigned char) (tmemclk >> 8));
335 write_hex ((unsigned char) (tmemclk));
341 for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) {
342 /* is this CAS latency supported ? */
343 if ((supported_cal >> i) & 0x01) {
344 buf[0] = datain[cal_indextable[cal_index]];
346 if (NS10to10PS (buf[0], spd_version) <= tmemclk)
349 /* SPD bytes 25+26 have another format */
350 if (NS4to10PS (buf[0], spd_version) <= tmemclk)
357 serial_puts ("CAL: ");
358 write_hex (cal_val + 1);
363 SDRAM_err ("unsupported SDRAM");
365 /* get SDRAM timing register */
366 mtdcr (memcfga, mem_sdtr1);
367 tmp = mfdcr (memcfgd) & ~0x018FC01F;
368 /* insert CASL value */
369 /* tmp |= ((unsigned long)cal_val) << 23; */
370 tmp |= ((unsigned long) cal_val) << 23;
371 /* insert PTA value */
372 tmp |= ((unsigned long) (trp_clocks - 1)) << 18;
373 /* insert CTP value */
374 /* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
375 tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16;
376 /* insert LDF (always 01) */
377 tmp |= ((unsigned long) 0x01) << 14;
378 /* insert RFTA value */
379 tmp |= ((unsigned long) (trc_clocks - 4)) << 2;
380 /* insert RCD value */
381 tmp |= ((unsigned long) (trcd_clocks - 1)) << 0;
384 serial_puts ("sdtr: ");
389 /* write SDRAM timing register */
390 mtdcr (memcfga, mem_sdtr1);
391 mtdcr (memcfgd, tmp);
392 baseaddr = CFG_SDRAM_BASE;
393 bank_size = (((unsigned long) density) << 22) / 2;
394 /* insert AM value */
395 tmp = ((unsigned long) t->mode - 1) << 13;
396 /* insert SZ value; */
399 tmp |= ((unsigned long) 0x00) << 17;
402 tmp |= ((unsigned long) 0x01) << 17;
405 tmp |= ((unsigned long) 0x02) << 17;
408 tmp |= ((unsigned long) 0x03) << 17;
411 tmp |= ((unsigned long) 0x04) << 17;
414 tmp |= ((unsigned long) 0x05) << 17;
417 tmp |= ((unsigned long) 0x06) << 17;
420 SDRAM_err ("unsupported SDRAM");
422 /* get SDRAM bank 0 register */
423 mtdcr (memcfga, mem_mb0cf);
424 bank = mfdcr (memcfgd) & ~0xFFCEE001;
425 bank |= (baseaddr | tmp | 0x01);
427 serial_puts ("bank0: baseaddr: ");
428 write_4hex (baseaddr);
429 serial_puts (" banksize: ");
430 write_4hex (bank_size);
431 serial_puts (" mb0cf: ");
435 baseaddr += bank_size;
436 sdram_size += bank_size;
438 /* write SDRAM bank 0 register */
439 mtdcr (memcfga, mem_mb0cf);
440 mtdcr (memcfgd, bank);
442 /* get SDRAM bank 1 register */
443 mtdcr (memcfga, mem_mb1cf);
444 bank = mfdcr (memcfgd) & ~0xFFCEE001;
448 serial_puts ("bank1: baseaddr: ");
449 write_4hex (baseaddr);
450 serial_puts (" banksize: ");
451 write_4hex (bank_size);
454 bank |= (baseaddr | tmp | 0x01);
455 baseaddr += bank_size;
456 sdram_size += bank_size;
459 serial_puts (" mb1cf: ");
463 /* write SDRAM bank 1 register */
464 mtdcr (memcfga, mem_mb1cf);
465 mtdcr (memcfgd, bank);
467 /* get SDRAM bank 2 register */
468 mtdcr (memcfga, mem_mb2cf);
469 bank = mfdcr (memcfgd) & ~0xFFCEE001;
471 bank |= (baseaddr | tmp | 0x01);
474 serial_puts ("bank2: baseaddr: ");
475 write_4hex (baseaddr);
476 serial_puts (" banksize: ");
477 write_4hex (bank_size);
478 serial_puts (" mb2cf: ");
483 baseaddr += bank_size;
484 sdram_size += bank_size;
486 /* write SDRAM bank 2 register */
487 mtdcr (memcfga, mem_mb2cf);
488 mtdcr (memcfgd, bank);
490 /* get SDRAM bank 3 register */
491 mtdcr (memcfga, mem_mb3cf);
492 bank = mfdcr (memcfgd) & ~0xFFCEE001;
495 serial_puts ("bank3: baseaddr: ");
496 write_4hex (baseaddr);
497 serial_puts (" banksize: ");
498 write_4hex (bank_size);
502 bank |= (baseaddr | tmp | 0x01);
503 baseaddr += bank_size;
504 sdram_size += bank_size;
508 serial_puts (" mb3cf: ");
513 /* write SDRAM bank 3 register */
514 mtdcr (memcfga, mem_mb3cf);
515 mtdcr (memcfgd, bank);
518 /* get SDRAM refresh interval register */
519 mtdcr (memcfga, mem_rtr);
520 tmp = mfdcr (memcfgd) & ~0x3FF80000;
522 if (tmemclk < NSto10PS (16))
527 /* write SDRAM refresh interval register */
528 mtdcr (memcfga, mem_rtr);
529 mtdcr (memcfgd, tmp);
531 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
532 mtdcr (memcfga, mem_mcopt1);
533 tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80E00000;
534 mtdcr (memcfga, mem_mcopt1);
535 mtdcr (memcfgd, tmp);
538 /*-------------------------------------------------------------------------+
539 | Interrupt controller setup for the PIP405 board.
540 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
541 | IRQ 16 405GP internally generated; active low; level sensitive
543 | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
544 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
545 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
546 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
547 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
548 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
549 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
550 | Note for PIP405 board:
551 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
552 | the Interrupt Controller in the South Bridge has caused the
553 | interrupt. The IC must be read to determine which device
554 | caused the interrupt.
556 +-------------------------------------------------------------------------*/
557 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
558 mtdcr (uicer, 0x00000000); /* disable all ints */
559 mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
560 mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
561 mtdcr (uictr, 0x10000000); /* set int trigger levels */
562 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
563 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
569 /* ------------------------------------------------------------------------- */
572 * Check Board Identity:
575 int checkboard (void)
580 backup_t *b = (backup_t *) s;
584 i = getenv_r ("serial#", s, 32);
585 if ((i == 0) || strncmp (s, "PIP405", 6)) {
586 get_backup_values (b);
587 if (strncmp (b->signature, "MPL\0", 4) != 0) {
588 puts ("### No HW ID - assuming PIP405");
590 b->serial_name[6] = 0;
591 printf ("%s SN: %s", b->serial_name,
596 printf ("%s SN: %s", s, &s[7]);
598 bc = in8 (CONFIG_PORT_ADDR);
599 printf (" Boot Config: 0x%x\n", bc);
604 /* ------------------------------------------------------------------------- */
605 /* ------------------------------------------------------------------------- */
607 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
608 the necessary info for SDRAM controller configuration
610 /* ------------------------------------------------------------------------- */
611 /* ------------------------------------------------------------------------- */
612 static int test_dram (unsigned long ramsize);
614 long int initdram (int board_type)
616 DECLARE_GLOBAL_DATA_PTR;
618 unsigned long bank_reg[4], tmp, bank_size;
620 unsigned long TotalSize;
623 /* since the DRAM controller is allready set up,
624 * calculate the size with the bank registers
626 mtdcr (memcfga, mem_mb0cf);
627 bank_reg[0] = mfdcr (memcfgd);
628 mtdcr (memcfga, mem_mb1cf);
629 bank_reg[1] = mfdcr (memcfgd);
630 mtdcr (memcfga, mem_mb2cf);
631 bank_reg[2] = mfdcr (memcfgd);
632 mtdcr (memcfga, mem_mb3cf);
633 bank_reg[3] = mfdcr (memcfgd);
635 for (i = 0; i < 4; i++) {
636 if ((bank_reg[i] & 0x1) == 0x1) {
637 tmp = (bank_reg[i] >> 17) & 0x7;
638 bank_size = 4 << tmp;
639 TotalSize += bank_size;
644 printf ("single-sided DIMM ");
646 printf ("double-sided DIMM ");
647 test_dram (TotalSize * 1024 * 1024);
648 /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
650 if (gd->cpu_clk > 220000000)
652 return (TotalSize * 1024 * 1024);
655 /* ------------------------------------------------------------------------- */
658 static int test_dram (unsigned long ramsize)
660 /* not yet implemented */
665 extern flash_info_t flash_info[]; /* info for FLASH chips */
667 int misc_init_r (void)
669 DECLARE_GLOBAL_DATA_PTR;
670 /* adjust flash start and size as well as the offset */
671 gd->bd->bi_flashstart=0-flash_info[0].size;
672 gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
673 gd->bd->bi_flashoffset=0;
675 /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
676 if (mfdcr(strap) & PSR_ROM_LOC)
677 mtspr(ccr0, (mfspr(ccr0) & ~0x80));
682 /***************************************************************************
683 * some helping routines
686 int overwrite_console (void)
688 return (in8 (CONFIG_PORT_ADDR) & 0x1); /* return TRUE if console should be overwritten */
692 extern int isa_init (void);
695 void print_pip405_rev (void)
697 unsigned char part, vers, cfg;
699 part = in8 (PLD_PART_REG);
700 vers = in8 (PLD_VERS_REG);
701 cfg = in8 (PLD_BOARD_CFG_REG);
702 printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
703 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf,
704 vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf);
707 extern void check_env(void);
710 int last_stage_init (void)
719 /************************************************************************
721 ************************************************************************/
722 void print_pip405_info (void)
724 unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr,
725 compwr, nicvga, scsirst;
727 part = in8 (PLD_PART_REG);
728 vers = in8 (PLD_VERS_REG);
729 cfg = in8 (PLD_BOARD_CFG_REG);
730 ledu = in8 (PLD_LED_USER_REG);
731 sysman = in8 (PLD_SYS_MAN_REG);
732 flashcom = in8 (PLD_FLASH_COM_REG);
733 can = in8 (PLD_CAN_REG);
734 serpwr = in8 (PLD_SER_PWR_REG);
735 compwr = in8 (PLD_COM_PWR_REG);
736 nicvga = in8 (PLD_NIC_VGA_REG);
737 scsirst = in8 (PLD_SCSI_RST_REG);
738 printf ("PLD Part %d version %d\n",
739 part & 0xf, vers & 0xf);
740 printf ("PLD Part %d version %d\n",
741 (part >> 4) & 0xf, (vers >> 4) & 0xf);
742 printf ("Board Revision %c\n", (cfg & 0xf) + 'A');
743 printf ("Population Options %d %d %d %d\n",
744 (cfg >> 4) & 0x1, (cfg >> 5) & 0x1,
745 (cfg >> 6) & 0x1, (cfg >> 7) & 0x1);
746 printf ("User LED0 %s User LED1 %s\n",
747 ((ledu & 0x1) == 0x1) ? "on" : "off",
748 ((ledu & 0x2) == 0x2) ? "on" : "off");
749 printf ("Additionally Options %d %d\n",
750 (ledu >> 2) & 0x1, (ledu >> 3) & 0x1);
751 printf ("User Config Switch %d %d %d %d\n",
752 (ledu >> 4) & 0x1, (ledu >> 5) & 0x1,
753 (ledu >> 6) & 0x1, (ledu >> 7) & 0x1);
754 switch (sysman & 0x3) {
756 printf ("PCI Clocks are running\n");
759 printf ("PCI Clocks are stopped in POS State\n");
762 printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
765 printf ("PCI Clocks are stopped\n");
768 switch ((sysman >> 2) & 0x3) {
770 printf ("Main Clocks are running\n");
773 printf ("Main Clocks are stopped in POS State\n");
777 printf ("PCI Clocks are stopped\n");
780 printf ("INIT asserts %sINT2# (SMI)\n",
781 ((sysman & 0x10) == 0x10) ? "" : "not ");
782 printf ("INIT asserts %sINT1# (NMI)\n",
783 ((sysman & 0x20) == 0x20) ? "" : "not ");
784 printf ("INIT occured %d\n", (sysman >> 6) & 0x1);
785 printf ("SER1 is routed to %s\n",
786 ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
787 printf ("COM2 is routed to %s\n",
788 ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232");
789 printf ("RS485 is configured as %s duplex\n",
790 ((flashcom & 0x4) == 0x4) ? "full" : "half");
791 printf ("RS485 is connected to %s\n",
792 ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2");
793 printf ("SER1 uses handshakes %s\n",
794 ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
795 printf ("Bootflash is %swriteprotected\n",
796 ((flashcom & 0x20) == 0x20) ? "not " : "");
797 printf ("Bootflash VPP is %s\n",
798 ((flashcom & 0x40) == 0x40) ? "on" : "off");
799 printf ("Bootsector is %swriteprotected\n",
800 ((flashcom & 0x80) == 0x80) ? "not " : "");
801 switch ((can) & 0x3) {
803 printf ("CAN Controller is on address 0x1000..0x10FF\n");
806 printf ("CAN Controller is on address 0x8000..0x80FF\n");
809 printf ("CAN Controller is on address 0xE000..0xE0FF\n");
812 printf ("CAN Controller is disabled\n");
815 switch ((can >> 2) & 0x3) {
817 printf ("CAN Controller Reset is ISA Reset\n");
820 printf ("CAN Controller Reset is ISA Reset and POS State\n");
824 printf ("CAN Controller is in reset\n");
827 if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13))
828 printf ("CAN Interrupt is disabled\n");
830 printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf);
831 switch (serpwr & 0x3) {
833 printf ("SER0 Drivers are enabled\n");
836 printf ("SER0 Drivers are disabled in the POS state\n");
840 printf ("SER0 Drivers are disabled\n");
843 switch ((serpwr >> 2) & 0x3) {
845 printf ("SER1 Drivers are enabled\n");
848 printf ("SER1 Drivers are disabled in the POS state\n");
852 printf ("SER1 Drivers are disabled\n");
855 switch (compwr & 0x3) {
857 printf ("COM1 Drivers are enabled\n");
860 printf ("COM1 Drivers are disabled in the POS state\n");
864 printf ("COM1 Drivers are disabled\n");
867 switch ((compwr >> 2) & 0x3) {
869 printf ("COM2 Drivers are enabled\n");
872 printf ("COM2 Drivers are disabled in the POS state\n");
876 printf ("COM2 Drivers are disabled\n");
879 switch ((nicvga) & 0x3) {
881 printf ("PHY is running\n");
884 printf ("PHY is in Power save mode in POS state\n");
888 printf ("PHY is in Power save mode\n");
891 switch ((nicvga >> 2) & 0x3) {
893 printf ("VGA is running\n");
896 printf ("VGA is in Power save mode in POS state\n");
900 printf ("VGA is in Power save mode\n");
903 printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not ");
904 printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not ");
905 printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1,
906 (nicvga >> 7) & 0x1);
907 switch ((scsirst) & 0x3) {
909 printf ("SCSI Controller is running\n");
912 printf ("SCSI Controller is in Power save mode in POS state\n");
916 printf ("SCSI Controller is in Power save mode\n");
919 printf ("SCSI termination is %s\n",
920 ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled");
921 printf ("SCSI Controller is %sreseted\n",
922 ((scsirst & 0x10) == 0x10) ? "" : "not ");
923 printf ("IDE disks are %sreseted\n",
924 ((scsirst & 0x20) == 0x20) ? "" : "not ");
925 printf ("ISA Bus is %sreseted\n",
926 ((scsirst & 0x40) == 0x40) ? "" : "not ");
927 printf ("Super IO is %sreseted\n",
928 ((scsirst & 0x80) == 0x80) ? "" : "not ");
931 void user_led0 (unsigned char on)
934 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
936 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
939 void user_led1 (unsigned char on)
942 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
944 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
947 void ide_set_reset (int idereset)
949 /* if reset = 1 IDE reset will be asserted */
950 unsigned char resreg;
952 resreg = in8 (PLD_SCSI_RST_REG);
959 out8 (PLD_SCSI_RST_REG, resreg);