3 * Mark Jonas <mark.jonas@de.bosch.com>
6 * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
8 * board/mpr2/lowlevel_init.S
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * Set frequency multipliers and dividers in FRQCR.
102 * Configuration for MPR2 A.3 through A.7
108 FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */
109 WTCNT_D: .long 0x5A00 /* start counting at zero */
110 WTCSR_D: .long 0xA507 /* divide by 4096 */
113 * Spansion S29GL256N11 @ 48 MHz
115 /* 1 idle cycle inserted, normal space, 16 bit */
116 CS0BCR_D: .long 0x12490400
117 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
118 CS0WCR_D: .long 0x00000340
121 * Samsung K4S511632B-UL75 @ 48 MHz
122 * Micron MT48LC32M16A2-75 @ 48 MHz
124 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
125 CS3BCR_D: .long 0x10004400
126 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
127 CS3WCR_D: .long 0x00000091
128 /* no refresh, 13 rows, 10 cols, NO bank active mode */
129 SDCR_D1: .long 0x00000012
130 SDCR_D2: .long 0x00000812 /* refresh */
131 RTCSR_D: .long 0xA55A0008 /* 1/4, once */
132 RTCNT_D: .long 0xA55A005D /* count 93 */
133 RTCOR_D: .long 0xa55a005d /* count 93 */
134 /* mode register CL2, burst read and SINGLE WRITE */
141 FRQCR_A: .long 0xA415FF80
142 WTCNT_A: .long 0xA415FF84
143 WTCSR_A: .long 0xA415FF86
145 #define BSC_BASE 0xA4FD0000
146 CS0BCR_A: .long BSC_BASE + 0x04
147 CS3BCR_A: .long BSC_BASE + 0x0C
148 CS0WCR_A: .long BSC_BASE + 0x24
149 CS3WCR_A: .long BSC_BASE + 0x2C
150 SDCR_A: .long BSC_BASE + 0x44
151 RTCSR_A: .long BSC_BASE + 0x48
152 RTCNT_A: .long BSC_BASE + 0x4C
153 RTCOR_A: .long BSC_BASE + 0x50
154 SDMR3_A: .long BSC_BASE + 0x5000