2 * GNU General Public License for more details.
4 * MATRIX Vision GmbH / June 2002-Nov 2003
17 u32 get_BoardType (void);
19 #define PCI_CONFIG(b,d,f,r) cpu_to_le32(0x80000000 | ((b&0xff)<<16) \
24 int mv_pci_read (int bus, int dev, int func, int reg)
26 *(u32 *) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg);
28 return cpu_to_le32 (*(u32 *) (0xfee00cfc));
33 return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1);
36 void init_2nd_DUART (void)
38 NS16550_t console = (NS16550_t) CFG_NS16550_COM2;
39 int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE;
41 *(u8 *) (0xfc004511) = 0x1;
42 NS16550_init (console, clock_divisor);
44 void hw_watchdog_reset (void)
46 if (get_BoardType () == 0) {
47 *(u32 *) (0xff000005) = 0;
53 DECLARE_GLOBAL_DATA_PTR;
54 ulong busfreq = get_bus_freq (0);
56 u32 BoardType = get_BoardType ();
57 char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
63 printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
64 printf (" Found %s running at %s MHz memory clock.\n",
65 BoardName[BoardType], strmhz (buf, busfreq));
69 if ((p = getenv ("console_nr")) != NULL) {
70 unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;
72 bd->bi_baudrate &= ~3;
73 bd->bi_baudrate |= con_nr & 3;
78 long int initdram (int board_type)
81 volatile uchar *base = CFG_SDRAM_BASE;
86 for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
88 addr = (volatile ulong *) base + cnt;
93 addr = (volatile ulong *) base;
102 for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
103 addr = (volatile ulong *) base + cnt;
107 ulong new_bank0_end = cnt * sizeof (long) - 1;
108 ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
109 ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
111 mear1 = (mear1 & 0xFFFFFF00) |
112 ((new_bank0_end & MICR_ADDR_MASK) >>
114 emear1 = (emear1 & 0xFFFFFF00) |
115 ((new_bank0_end & MICR_ADDR_MASK) >>
117 mpc824x_mpc107_setreg (MEAR1, mear1);
118 mpc824x_mpc107_setreg (EMEAR1, emear1);
119 ret = cnt * sizeof (long);
124 ret = CFG_MAX_RAM_SIZE;
129 /* ------------------------------------------------------------------------- */
130 u8 *dhcp_vendorex_prep (u8 * e)
134 /* DHCP vendor-class-identifier = 60 */
135 if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
141 /* my DHCP_CLIENT_IDENTIFIER = 61 */
142 if ((ptr = getenv ("dhcp_client_id"))) {
151 u8 *dhcp_vendorex_proc (u8 * popt)
156 /* ------------------------------------------------------------------------- */
159 * Initialize PCI Devices
162 void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev)
166 printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev),
168 for (cnt = 0; cnt < 6; cnt++)
169 pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt),
174 void duart_setup (u32 base, u16 divisor)
176 printf ("duart setup ...");
177 out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x80);
178 out_8 ((u8 *) (CFG_ISA_IO + base + 0), divisor & 0xff);
179 out_8 ((u8 *) (CFG_ISA_IO + base + 1), divisor >> 8);
180 out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x03);
181 out_8 ((u8 *) (CFG_ISA_IO + base + 4), 0x03);
182 out_8 ((u8 *) (CFG_ISA_IO + base + 2), 0x07);
186 void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose,
187 pci_dev_t bridge, unsigned char irq)
191 unsigned short vendor, class;
193 pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus);
194 for (d = PCI_BDF (bus, 0, 0);
195 d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1,
196 PCI_MAX_PCI_FUNCTIONS - 1);
197 d += PCI_BDF (0, 0, 1)) {
198 pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor);
199 if (vendor != 0xffff && vendor != 0x0000) {
200 pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE,
202 if (class == PCI_CLASS_BRIDGE_PCI)
203 pci_mvblue_fixup_irq_behind_bridge (hose, d,
206 pci_hose_write_config_byte (hose, d,
213 #define MV_MAX_PCI_BUSSES 3
216 void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
218 unsigned char line = 0xff;
219 unsigned short class;
221 if (PCI_BUS (dev) == 0) {
222 switch (PCI_DEV (dev)) {
224 if (get_BoardType () == 0) {
233 pci_hose_write_config_byte (hose, dev, 0x8a, 0x20);
236 /* mvBB: Slot0 (Grabber) */
237 pci_hose_read_config_word (hose, dev,
238 PCI_CLASS_DEVICE, &class);
239 if (class == PCI_CLASS_BRIDGE_PCI) {
240 pci_mvblue_fixup_irq_behind_bridge (hose, dev,
248 pci_hose_read_config_word (hose, dev,
249 PCI_CLASS_DEVICE, &class);
250 if (class == PCI_CLASS_BRIDGE_PCI) {
251 pci_mvblue_fixup_irq_behind_bridge (hose, dev,
258 printf ("***pci_scan: illegal dev = 0x%08x\n",
263 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE,
268 struct pci_controller hose = {
269 fixup_irq:pci_mvblue_fixup_irq
272 void pci_init_board (void)
274 pci_mpc824x_init (&hose);