3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
5 * (C) Copyright 2001-2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /* ------------------------------------------------------------------------- */
33 static long int dram_size (long int, long int *, long int);
35 /* ------------------------------------------------------------------------- */
37 #define _NOT_USED_ 0xFFFFFFFF
39 const uint sdram_table[] =
41 #if (MPC8XX_SPEED <= 50000000L)
43 * Single Read. (Offset 0 in UPMA RAM)
52 * SDRAM Initialization (offset 5 in UPMA RAM)
54 * This is no UPM entry point. The following definition uses
55 * the remaining space to establish an initialization
56 * sequence, which is executed by a RUN command.
64 * Burst Read. (Offset 8 in UPMA RAM)
84 * Single Write. (Offset 18 in UPMA RAM)
96 * Burst Write. (Offset 20 in UPMA RAM)
116 * Refresh (Offset 30 in UPMA RAM)
132 * Exception. (Offset 3c in UPMA RAM)
142 * Single Read. (Offset 0 in UPMA RAM)
151 * SDRAM Initialization (offset 5 in UPMA RAM)
153 * This is no UPM entry point. The following definition uses
154 * the remaining space to establish an initialization
155 * sequence, which is executed by a RUN command.
163 * Burst Read. (Offset 8 in UPMA RAM)
173 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
174 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
177 * Single Write. (Offset 18 in UPMA RAM)
183 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
186 * Burst Write. (Offset 20 in UPMA RAM)
195 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
196 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
199 * Refresh (Offset 30 in UPMA RAM)
207 _NOT_USED_, _NOT_USED_, _NOT_USED_,
208 _NOT_USED_, _NOT_USED_, _NOT_USED_,
211 * Exception. (Offset 3c in UPMA RAM)
213 0x7FFFFC07, /* last */
214 _NOT_USED_, _NOT_USED_, _NOT_USED_,
218 /* ------------------------------------------------------------------------- */
222 * Check Board Identity:
226 int checkboard (void)
228 printf ("Board: Nexus NX823");
232 /* ------------------------------------------------------------------------- */
234 long int initdram (int board_type)
236 volatile immap_t *immap = (immap_t *)CFG_IMMR;
237 volatile memctl8xx_t *memctl = &immap->im_memctl;
238 long int size_b0, size_b1, size8, size9;
240 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
243 * Up to 2 Banks of 64Mbit x 2 devices
244 * Initial builds only have 1
246 memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
247 memctl->memc_mar = 0x00000088;
250 * Map controller SDRAM bank 0
252 memctl->memc_or1 = CFG_OR1_PRELIM;
253 memctl->memc_br1 = CFG_BR1_PRELIM;
254 memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
258 * Map controller SDRAM bank 1
260 memctl->memc_or2 = CFG_OR2_PRELIM;
261 memctl->memc_br2 = CFG_BR2_PRELIM;
264 * Perform SDRAM initializsation sequence
266 memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
268 memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
271 memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
273 memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */
276 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
280 * Preliminary prescaler for refresh (depends on number of
281 * banks): This value is selected for four cycles every 62.4 us
282 * with two SDRAM banks or four cycles every 31.2 us with one
283 * bank. It will be adjusted after memory sizing.
285 memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
287 memctl->memc_mar = 0x00000088;
291 * Check Bank 0 Memory Size for re-configuration
295 size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
302 size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
304 if (size8 < size9) { /* leave configuration at 9 columns */
306 /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
307 } else { /* back to 8 columns */
309 memctl->memc_mamr = CFG_MAMR_8COL;
311 /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
315 * Check Bank 1 Memory Size
316 * use current column settings
317 * [9 column SDRAM may also be used in 8 column mode,
318 * but then only half the real size will be used.]
320 size_b1 = dram_size (memctl->memc_mamr, (ulong *)SDRAM_BASE2_PRELIM,
322 /* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
327 * Adjust refresh rate depending on SDRAM type, both banks
328 * For types > 128 MBit leave it at the current (fast) rate
330 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
331 /* reduce to 15.6 us (62.4 us / quad) */
332 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
337 * Final mapping: map bigger bank first
339 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
341 memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
342 memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
346 * Position Bank 0 immediately above Bank 1
348 memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
349 memctl->memc_br1 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
358 memctl->memc_br1 = 0;
360 /* adjust refresh rate depending on SDRAM type, one bank */
361 reg = memctl->memc_mptpr;
362 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
363 memctl->memc_mptpr = reg;
366 } else { /* SDRAM Bank 0 is bigger - map first */
368 memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
369 memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
373 * Position Bank 1 immediately above Bank 0
375 memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
376 memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
385 memctl->memc_br2 = 0;
387 /* adjust refresh rate depending on SDRAM type, one bank */
388 reg = memctl->memc_mptpr;
389 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
390 memctl->memc_mptpr = reg;
396 return (size_b0 + size_b1);
399 /* ------------------------------------------------------------------------- */
402 * Check memory range for valid RAM. A simple memory test determines
403 * the actually available RAM size between addresses `base' and
404 * `base + maxsize'. Some (not all) hardware errors are detected:
405 * - short between address lines
406 * - short between data lines
409 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
411 volatile immap_t *immap = (immap_t *)CFG_IMMR;
412 volatile memctl8xx_t *memctl = &immap->im_memctl;
413 volatile long int *addr;
416 memctl->memc_mamr = mamr_value;
418 for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
419 addr = base + cnt; /* pointer arith! */
424 /* write 0 to base address */
428 /* check at base address */
429 if ((val = *addr) != 0) {
433 for (cnt = 1; ; cnt <<= 1) {
434 addr = base + cnt; /* pointer arith! */
439 return (cnt * sizeof(long));
447 int misc_init_r (void)
449 DECLARE_GLOBAL_DATA_PTR;
452 u_char *e = gd->bd->bi_enetaddr;
454 /* save serial numbre from flash (uniquely programmed) */
455 my_sernum = malloc(8);
456 memcpy(my_sernum,gd->bd->bi_sernum,8);
458 /* save env variables according to sernum */
459 sprintf(tmp,"%08lx%08lx",my_sernum[0],my_sernum[1]);
460 setenv("serial#",tmp);
462 sprintf(tmp,"%02x:%02x:%02x:%02x:%02x:%02x"
463 ,e[0],e[1],e[2],e[3],e[4],e[5]);
464 setenv("ethaddr",tmp);
468 void load_sernum_ethaddr (void)
470 DECLARE_GLOBAL_DATA_PTR;
475 for (i = 0; i < 8; i++) {
476 bd->bi_sernum[i] = *(u_char *) (CFG_FLASH_SN_BASE + i);
478 bd->bi_enetaddr[0] = 0x10;
479 bd->bi_enetaddr[1] = 0x20;
480 bd->bi_enetaddr[2] = 0x30;
481 bd->bi_enetaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2];
482 bd->bi_enetaddr[4] = bd->bi_sernum[5];
483 bd->bi_enetaddr[5] = bd->bi_sernum[6];