3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <linux/mtd/doc2000.h>
35 #include "fpga_serial.h"
37 #if defined(CONFIG_WATCHDOG)
39 static int pcippc2_wdt_init_done = 0;
41 void pcippc2_wdt_init (void);
45 /* Check board identity
50 puts ("Board: Gespac PCIPPC-2\n");
52 puts ("Board: Gespac PCIPPC-6\n");
57 /* RAM size is stored in CPC0_RGBAN1
59 u32 pcippc2_sdram_size (void)
61 return in32 (REG (CPC0, RGBAN1));
64 long initdram (int board_type)
66 return cpc710_ram_init ();
69 void do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
71 out32 (REG (CPC0, SPOR), 0);
76 int board_pre_init (void)
78 out32 (REG (CPC0, RSTR), 0xC0000000);
81 out32 (REG (CPC0, RSTR), 0xF0000000);
84 out32 (REG (CPC0, UCTL), 0x00F80000);
86 out32 (REG (CPC0, SIOC0), 0x30000000);
88 out32 (REG (CPC0, ABCNTL), 0x00000000);
90 out32 (REG (CPC0, SESR), 0x00000000);
91 out32 (REG (CPC0, SEAR), 0x00000000);
93 /* Detect IBM Avignon CPC710 Revision */
94 if ((in32 (REG (CPC0, UCTL)) & 0x000000F0) == CPC710_TYPE_100P)
95 out32 (REG (CPC0, PGCHP), 0xA0000040);
97 out32 (REG (CPC0, PGCHP), 0x80800040);
100 out32 (REG (CPC0, ATAS), 0x709C2508);
107 void after_reloc (ulong dest_addr)
109 DECLARE_GLOBAL_DATA_PTR;
111 /* Jump to the main U-Boot board init code
113 board_init_r (gd, dest_addr);
116 int misc_init_r (void)
118 pcippc2_fpga_init ();
120 pcippc2_cpci3264_init ();
122 #if defined(CONFIG_WATCHDOG)
126 fpga_serial_init (sconsole_get_baudrate ());
128 sconsole_putc = fpga_serial_putc;
129 sconsole_puts = fpga_serial_puts;
130 sconsole_getc = fpga_serial_getc;
131 sconsole_tstc = fpga_serial_tstc;
132 sconsole_setbrg = fpga_serial_setbrg;
142 /* FPGA requires no retry timeouts to be enabled
144 cpc710_pci_enable_timeout ();
149 doc_probe (pcippc2_fpga1_phys + HW_FPGA1_DOC);
152 void pcippc2_cpci3264_init (void)
154 pci_dev_t bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0);
158 puts("Unable to find FPGA !\n");
162 if((in32(pcippc2_fpga0_phys + HW_FPGA0_BOARD) & 0x01000000) == 0x01000000)
163 /* 32-bits Compact PCI bus - LSB bit */
166 out32(BRIDGE(CPCI, PCIDG), 0x40000000); /* 32-bits bridge, Pipeline */
171 #if defined(CONFIG_WATCHDOG)
173 void pcippc2_wdt_init (void)
175 out16r (FPGA (WDT, PROG), 0xffff);
176 out8 (FPGA (WDT, CTRL), 0x1);
178 pcippc2_wdt_init_done = 1;
181 void pcippc2_wdt_done (void)
183 out8 (FPGA (WDT, CTRL), 0x0);
185 pcippc2_wdt_init_done = 0;
188 void pcippc2_wdt_reset (void)
190 if (pcippc2_wdt_init_done == 1)
191 out8 (FPGA (WDT, REFRESH), 0x56);
194 void watchdog_reset (void)
196 int re_enable = disable_interrupts ();
198 pcippc2_wdt_reset ();
200 enable_interrupts ();
203 #if (CONFIG_COMMANDS & CFG_CMD_BSP)
204 int do_wd (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
208 printf ("Watchdog timer status is %s\n",
209 pcippc2_wdt_init_done == 1 ? "on" : "off");
213 if (!strcmp(argv[1],"on")) {
215 printf("Watchdog timer now is on\n");
219 } else if (!strcmp(argv[1],"off")) {
221 printf("Watchdog timer now is off\n");
230 printf ("Usage:\n%s\n", cmdtp->usage);
234 #endif /* CFG_CMD_BSP */
235 #endif /* CONFIG_WATCHDOG */