4 * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
6 * Copyright (C) 2013 Lemonage Software GmbH
7 * Author Lars Poeschel <poeschel@lemonage.de>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
17 * GNU General Public License for more details.
23 #include <asm/arch/cpu.h>
24 #include <asm/arch/hardware.h>
25 #include <asm/arch/omap.h>
26 #include <asm/arch/ddr_defs.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc_host_def.h>
30 #include <asm/arch/sys_proto.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
42 #ifdef CONFIG_SPL_BUILD
43 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
46 /* MII mode defines */
47 #define MII_MODE_ENABLE 0x0
48 #define RGMII_MODE_ENABLE 0xA
49 #define RMII_RGMII2_MODE_ENABLE 0x49
51 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
54 #ifdef CONFIG_SPL_BUILD
55 #define UART_RESET (0x1 << 1)
56 #define UART_CLK_RUNNING_MASK 0x1
57 #define UART_SMART_IDLE_EN (0x1 << 0x3)
60 #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
62 static const struct ddr_data ddr3_data = {
63 .datardsratio0 = MT41J256M8HX15E_RD_DQS,
64 .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
65 .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
66 .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
67 .datadldiff0 = PHY_DLL_LOCK_DIFF,
70 static const struct cmd_control ddr3_cmd_ctrl_data = {
71 .cmd0csratio = MT41J256M8HX15E_RATIO,
72 .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
73 .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
75 .cmd1csratio = MT41J256M8HX15E_RATIO,
76 .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
77 .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
79 .cmd2csratio = MT41J256M8HX15E_RATIO,
80 .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
81 .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
84 static struct emif_regs ddr3_emif_reg_data = {
85 .sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
86 .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
87 .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
88 .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
89 .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
90 .zq_config = MT41J256M8HX15E_ZQ_CFG,
91 .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
97 * early system init of muxing and clocks.
102 * Save the boot parameters passed from romcode.
103 * We cannot delay the saving further than this,
104 * to prevent overwrites.
106 #ifdef CONFIG_SPL_BUILD
107 save_omap_boot_params();
111 * WDT1 is already running when the bootloader gets control
112 * Disable it to avoid "random" resets
114 writel(0xAAAA, &wdtimer->wdtwspr);
115 while (readl(&wdtimer->wdtwwps) != 0x0)
117 writel(0x5555, &wdtimer->wdtwspr);
118 while (readl(&wdtimer->wdtwwps) != 0x0)
121 #ifdef CONFIG_SPL_BUILD
122 /* Setup the PLLs and the clocks for the peripherals */
125 /* Enable RTC32K clock */
131 enable_uart0_pin_mux();
133 regval = readl(&uart_base->uartsyscfg);
134 regval |= UART_RESET;
135 writel(regval, &uart_base->uartsyscfg);
136 while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK)
137 != UART_CLK_RUNNING_MASK)
140 /* Disable smart idle */
141 regval = readl(&uart_base->uartsyscfg);
142 regval |= UART_SMART_IDLE_EN;
143 writel(regval, &uart_base->uartsyscfg);
147 preloader_console_init();
149 /* Initalize the board header */
150 enable_i2c0_pin_mux();
151 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
153 enable_board_pin_mux();
155 config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
156 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
161 * Basic board specific setup. Pinmux has been handled already.
165 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
167 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
172 #ifdef CONFIG_DRIVER_TI_CPSW
173 static void cpsw_control(int enabled)
175 /* VTP can be added here */
180 static struct cpsw_slave_data cpsw_slaves[] = {
182 .slave_reg_ofs = 0x208,
183 .sliver_reg_ofs = 0xd80,
185 .phy_if = PHY_INTERFACE_MODE_RGMII,
188 .slave_reg_ofs = 0x308,
189 .sliver_reg_ofs = 0xdc0,
191 .phy_if = PHY_INTERFACE_MODE_RGMII,
195 static struct cpsw_platform_data cpsw_data = {
196 .mdio_base = CPSW_MDIO_BASE,
197 .cpsw_base = CPSW_BASE,
200 .cpdma_reg_ofs = 0x800,
202 .slave_data = cpsw_slaves,
203 .ale_reg_ofs = 0xd00,
205 .host_port_reg_ofs = 0x108,
206 .hw_stats_reg_ofs = 0x900,
207 .mac_control = (1 << 5),
208 .control = cpsw_control,
210 .version = CPSW_CTRL_VERSION_2,
214 #if defined(CONFIG_DRIVER_TI_CPSW) || \
215 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
216 int board_eth_init(bd_t *bis)
219 #ifdef CONFIG_DRIVER_TI_CPSW
221 uint32_t mac_hi, mac_lo;
223 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
224 printf("<ethaddr> not set. Reading from E-fuse\n");
225 /* try reading mac address from efuse */
226 mac_lo = readl(&cdev->macid0l);
227 mac_hi = readl(&cdev->macid0h);
228 mac_addr[0] = mac_hi & 0xFF;
229 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
230 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
231 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
232 mac_addr[4] = mac_lo & 0xFF;
233 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
235 if (is_valid_ether_addr(mac_addr))
236 eth_setenv_enetaddr("ethaddr", mac_addr);
241 writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
243 rv = cpsw_register(&cpsw_data);
245 printf("Error %d registering CPSW switch\n", rv);
251 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
252 rv = usb_eth_initialize(bis);
254 printf("Error %d registering USB_ETHER\n", rv);