4 * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
6 * Copyright (C) 2013 Lemonage Software GmbH
7 * Author Lars Poeschel <poeschel@lemonage.de>
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/omap.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/mmc_host_def.h>
22 #include <asm/arch/sys_proto.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 /* MII mode defines */
34 #define MII_MODE_ENABLE 0x0
35 #define RGMII_MODE_ENABLE 0xA
36 #define RMII_RGMII2_MODE_ENABLE 0x49
38 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
40 #ifdef CONFIG_SPL_BUILD
43 #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
45 #define OSC (V_OSCK/1000000)
46 const struct dpll_params dpll_ddr = {
47 DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
49 const struct dpll_params *get_dpll_ddr_params(void)
54 static const struct ddr_data ddr3_data = {
55 .datardsratio0 = MT41J256M8HX15E_RD_DQS,
56 .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
57 .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
58 .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
59 .datadldiff0 = PHY_DLL_LOCK_DIFF,
62 static const struct cmd_control ddr3_cmd_ctrl_data = {
63 .cmd0csratio = MT41J256M8HX15E_RATIO,
64 .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
65 .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
67 .cmd1csratio = MT41J256M8HX15E_RATIO,
68 .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
69 .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
71 .cmd2csratio = MT41J256M8HX15E_RATIO,
72 .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
73 .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
76 static struct emif_regs ddr3_emif_reg_data = {
77 .sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
78 .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
79 .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
80 .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
81 .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
82 .zq_config = MT41J256M8HX15E_ZQ_CFG,
83 .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
87 void set_uart_mux_conf(void)
89 enable_uart0_pin_mux();
92 void set_mux_conf_regs(void)
94 /* Initalize the board header */
95 enable_i2c0_pin_mux();
96 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
98 enable_board_pin_mux();
101 void sdram_init(void)
103 config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
104 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
109 * Basic board specific setup. Pinmux has been handled already.
113 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
115 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
120 #ifdef CONFIG_DRIVER_TI_CPSW
121 static void cpsw_control(int enabled)
123 /* VTP can be added here */
128 static struct cpsw_slave_data cpsw_slaves[] = {
130 .slave_reg_ofs = 0x208,
131 .sliver_reg_ofs = 0xd80,
133 .phy_if = PHY_INTERFACE_MODE_RGMII,
136 .slave_reg_ofs = 0x308,
137 .sliver_reg_ofs = 0xdc0,
139 .phy_if = PHY_INTERFACE_MODE_RGMII,
143 static struct cpsw_platform_data cpsw_data = {
144 .mdio_base = CPSW_MDIO_BASE,
145 .cpsw_base = CPSW_BASE,
148 .cpdma_reg_ofs = 0x800,
150 .slave_data = cpsw_slaves,
151 .ale_reg_ofs = 0xd00,
153 .host_port_reg_ofs = 0x108,
154 .hw_stats_reg_ofs = 0x900,
155 .mac_control = (1 << 5),
156 .control = cpsw_control,
158 .version = CPSW_CTRL_VERSION_2,
162 #if defined(CONFIG_DRIVER_TI_CPSW) || \
163 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
164 int board_eth_init(bd_t *bis)
167 #ifdef CONFIG_DRIVER_TI_CPSW
169 uint32_t mac_hi, mac_lo;
171 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
172 printf("<ethaddr> not set. Reading from E-fuse\n");
173 /* try reading mac address from efuse */
174 mac_lo = readl(&cdev->macid0l);
175 mac_hi = readl(&cdev->macid0h);
176 mac_addr[0] = mac_hi & 0xFF;
177 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
178 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
179 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
180 mac_addr[4] = mac_lo & 0xFF;
181 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
183 if (is_valid_ether_addr(mac_addr))
184 eth_setenv_enetaddr("ethaddr", mac_addr);
189 writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
191 rv = cpsw_register(&cpsw_data);
193 printf("Error %d registering CPSW switch\n", rv);
199 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
200 rv = usb_eth_initialize(bis);
202 printf("Error %d registering USB_ETHER\n", rv);