4 * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
6 * Copyright (C) 2013 Lemonage Software GmbH
7 * Author Lars Poeschel <poeschel@lemonage.de>
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/omap.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/mmc_host_def.h>
22 #include <asm/arch/sys_proto.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
35 /* MII mode defines */
36 #define MII_MODE_ENABLE 0x0
37 #define RGMII_MODE_ENABLE 0xA
38 #define RMII_RGMII2_MODE_ENABLE 0x49
40 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
42 #ifdef CONFIG_SPL_BUILD
45 #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
47 static const struct ddr_data ddr3_data = {
48 .datardsratio0 = MT41J256M8HX15E_RD_DQS,
49 .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
50 .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
51 .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
52 .datadldiff0 = PHY_DLL_LOCK_DIFF,
55 static const struct cmd_control ddr3_cmd_ctrl_data = {
56 .cmd0csratio = MT41J256M8HX15E_RATIO,
57 .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
58 .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
60 .cmd1csratio = MT41J256M8HX15E_RATIO,
61 .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
62 .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
64 .cmd2csratio = MT41J256M8HX15E_RATIO,
65 .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
66 .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
69 static struct emif_regs ddr3_emif_reg_data = {
70 .sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
71 .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
72 .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
73 .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
74 .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
75 .zq_config = MT41J256M8HX15E_ZQ_CFG,
76 .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
82 * early system init of muxing and clocks.
87 * Save the boot parameters passed from romcode.
88 * We cannot delay the saving further than this,
89 * to prevent overwrites.
91 #ifdef CONFIG_SPL_BUILD
92 save_omap_boot_params();
96 * WDT1 is already running when the bootloader gets control
97 * Disable it to avoid "random" resets
99 writel(0xAAAA, &wdtimer->wdtwspr);
100 while (readl(&wdtimer->wdtwwps) != 0x0)
102 writel(0x5555, &wdtimer->wdtwspr);
103 while (readl(&wdtimer->wdtwwps) != 0x0)
106 #ifdef CONFIG_SPL_BUILD
107 /* Setup the PLLs and the clocks for the peripherals */
110 /* Enable RTC32K clock */
113 enable_uart0_pin_mux();
118 preloader_console_init();
120 /* Initalize the board header */
121 enable_i2c0_pin_mux();
122 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
124 enable_board_pin_mux();
126 config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
127 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
132 * Basic board specific setup. Pinmux has been handled already.
136 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
138 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
143 #ifdef CONFIG_DRIVER_TI_CPSW
144 static void cpsw_control(int enabled)
146 /* VTP can be added here */
151 static struct cpsw_slave_data cpsw_slaves[] = {
153 .slave_reg_ofs = 0x208,
154 .sliver_reg_ofs = 0xd80,
156 .phy_if = PHY_INTERFACE_MODE_RGMII,
159 .slave_reg_ofs = 0x308,
160 .sliver_reg_ofs = 0xdc0,
162 .phy_if = PHY_INTERFACE_MODE_RGMII,
166 static struct cpsw_platform_data cpsw_data = {
167 .mdio_base = CPSW_MDIO_BASE,
168 .cpsw_base = CPSW_BASE,
171 .cpdma_reg_ofs = 0x800,
173 .slave_data = cpsw_slaves,
174 .ale_reg_ofs = 0xd00,
176 .host_port_reg_ofs = 0x108,
177 .hw_stats_reg_ofs = 0x900,
178 .mac_control = (1 << 5),
179 .control = cpsw_control,
181 .version = CPSW_CTRL_VERSION_2,
185 #if defined(CONFIG_DRIVER_TI_CPSW) || \
186 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
187 int board_eth_init(bd_t *bis)
190 #ifdef CONFIG_DRIVER_TI_CPSW
192 uint32_t mac_hi, mac_lo;
194 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
195 printf("<ethaddr> not set. Reading from E-fuse\n");
196 /* try reading mac address from efuse */
197 mac_lo = readl(&cdev->macid0l);
198 mac_hi = readl(&cdev->macid0h);
199 mac_addr[0] = mac_hi & 0xFF;
200 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
201 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
202 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
203 mac_addr[4] = mac_lo & 0xFF;
204 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
206 if (is_valid_ether_addr(mac_addr))
207 eth_setenv_enetaddr("ethaddr", mac_addr);
212 writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
214 rv = cpsw_register(&cpsw_data);
216 printf("Error %d registering CPSW switch\n", rv);
222 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
223 rv = usb_eth_initialize(bis);
225 printf("Error %d registering USB_ETHER\n", rv);