2 * board/renesas/alt/alt.c
4 * Copyright (C) 2014, 2015 Renesas Electronics Corporation
6 * SPDX-License-Identifier: GPL-2.0
12 #include <dm/platform_data/serial_sh.h>
13 #include <environment.h>
14 #include <asm/processor.h>
15 #include <asm/mach-types.h>
17 #include <linux/errno.h>
18 #include <asm/arch/sys_proto.h>
20 #include <asm/arch/rmobile.h>
21 #include <asm/arch/rcar-mstp.h>
22 #include <asm/arch/mmc.h>
23 #include <asm/arch/sh_sdhi.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #define CLK2MHZ(clk) (clk / 1000 / 1000)
35 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
36 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
39 writel(0xA5A5A500, &rwdt->rwtcsra);
40 writel(0xA5A5A500, &swdt->swtcsra);
46 #define TMU0_MSTP125 (1 << 25)
47 #define SCIF2_MSTP719 (1 << 19)
48 #define ETHER_MSTP813 (1 << 13)
49 #define IIC1_MSTP323 (1 << 23)
50 #define MMC0_MSTP315 (1 << 15)
51 #define SDHI0_MSTP314 (1 << 14)
52 #define SDHI1_MSTP312 (1 << 12)
54 #define SD1CKCR 0xE6150078
55 #define SD1_97500KHZ 0x7
57 int board_early_init_f(void)
60 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
63 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
66 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
68 /* IIC1 / sh-i2c ch1 */
69 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
71 #ifdef CONFIG_SH_MMCIF
73 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
78 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI1_MSTP312);
81 * SD0 clock is set to 97.5MHz by default.
82 * Set SD1 to the 97.5MHz as well.
84 writel(SD1_97500KHZ, SD1CKCR);
91 /* adress of boot parameters */
92 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
94 /* Init PFC controller */
95 r8a7794_pinmux_init();
98 #if defined(CONFIG_R8A7794_ETHERNET_B)
99 gpio_request(GPIO_FN_ETH_CRS_DV_B, NULL);
100 gpio_request(GPIO_FN_ETH_RX_ER_B, NULL);
101 gpio_request(GPIO_FN_ETH_RXD0_B, NULL);
102 gpio_request(GPIO_FN_ETH_RXD1_B, NULL);
103 gpio_request(GPIO_FN_ETH_LINK_B, NULL);
104 gpio_request(GPIO_FN_ETH_REFCLK_B, NULL);
105 gpio_request(GPIO_FN_ETH_MDIO_B, NULL);
106 gpio_request(GPIO_FN_ETH_TXD1_B, NULL);
107 gpio_request(GPIO_FN_ETH_TX_EN_B, NULL);
108 gpio_request(GPIO_FN_ETH_MAGIC_B, NULL);
109 gpio_request(GPIO_FN_ETH_TXD0_B, NULL);
110 gpio_request(GPIO_FN_ETH_MDC_B, NULL);
112 gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
113 gpio_request(GPIO_FN_ETH_RX_ER, NULL);
114 gpio_request(GPIO_FN_ETH_RXD0, NULL);
115 gpio_request(GPIO_FN_ETH_RXD1, NULL);
116 gpio_request(GPIO_FN_ETH_LINK, NULL);
117 gpio_request(GPIO_FN_ETH_REFCLK, NULL);
118 gpio_request(GPIO_FN_ETH_MDIO, NULL);
119 gpio_request(GPIO_FN_ETH_TXD1, NULL);
120 gpio_request(GPIO_FN_ETH_TX_EN, NULL);
121 gpio_request(GPIO_FN_ETH_MAGIC, NULL);
122 gpio_request(GPIO_FN_ETH_TXD0, NULL);
123 gpio_request(GPIO_FN_ETH_MDC, NULL);
125 gpio_request(GPIO_FN_IRQ8, NULL);
128 gpio_request(GPIO_GP_1_24, NULL);
129 gpio_direction_output(GPIO_GP_1_24, 0);
131 gpio_set_value(GPIO_GP_1_24, 1);
137 #define CXR24 0xEE7003C0 /* MAC address high register */
138 #define CXR25 0xEE7003C8 /* MAC address low register */
139 int board_eth_init(bd_t *bis)
141 #ifdef CONFIG_SH_ETHER
144 unsigned char enetaddr[6];
146 ret = sh_eth_initialize(bis);
147 if (!eth_env_get_enetaddr("ethaddr", enetaddr))
150 /* Set Mac address */
151 val = enetaddr[0] << 24 | enetaddr[1] << 16 |
152 enetaddr[2] << 8 | enetaddr[3];
155 val = enetaddr[4] << 8 | enetaddr[5];
164 int board_mmc_init(bd_t *bis)
168 #ifdef CONFIG_SH_MMCIF
169 gpio_request(GPIO_GP_4_31, NULL);
170 gpio_set_value(GPIO_GP_4_31, 1);
172 ret = mmcif_mmc_init();
175 #ifdef CONFIG_SH_SDHI
176 gpio_request(GPIO_FN_SD0_DATA0, NULL);
177 gpio_request(GPIO_FN_SD0_DATA1, NULL);
178 gpio_request(GPIO_FN_SD0_DATA2, NULL);
179 gpio_request(GPIO_FN_SD0_DATA3, NULL);
180 gpio_request(GPIO_FN_SD0_CLK, NULL);
181 gpio_request(GPIO_FN_SD0_CMD, NULL);
182 gpio_request(GPIO_FN_SD0_CD, NULL);
183 gpio_request(GPIO_FN_SD1_DATA0, NULL);
184 gpio_request(GPIO_FN_SD1_DATA1, NULL);
185 gpio_request(GPIO_FN_SD1_DATA2, NULL);
186 gpio_request(GPIO_FN_SD1_DATA3, NULL);
187 gpio_request(GPIO_FN_SD1_CLK, NULL);
188 gpio_request(GPIO_FN_SD1_CMD, NULL);
189 gpio_request(GPIO_FN_SD1_CD, NULL);
192 gpio_request(GPIO_GP_2_26, NULL);
193 gpio_request(GPIO_GP_2_29, NULL);
194 gpio_direction_output(GPIO_GP_2_26, 1);
195 gpio_direction_output(GPIO_GP_2_29, 1);
197 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
198 SH_SDHI_QUIRK_16BIT_BUF);
203 gpio_request(GPIO_GP_4_26, NULL);
204 gpio_request(GPIO_GP_4_29, NULL);
205 gpio_direction_output(GPIO_GP_4_26, 1);
206 gpio_direction_output(GPIO_GP_4_29, 1);
208 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
215 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
220 const struct rmobile_sysinfo sysinfo = {
221 CONFIG_ARCH_RMOBILE_BOARD_STRING
224 void reset_cpu(ulong addr)
228 i2c_set_bus_num(1); /* PowerIC connected to ch1 */
229 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
231 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
234 static const struct sh_serial_platdata serial_platdata = {
241 U_BOOT_DEVICE(alt_serials) = {
243 .platdata = &serial_platdata,