git.sur5r.net Git - u-boot/blob - board/renesas/ecovec/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2011 Renesas Solutions Corp.
   3  * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
   4  *
   5  * board/renesas/ecovec/lowlevel_init.S
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <config.h>
  11 #include <asm/processor.h>
  12 #include <asm/macro.h>
  13 #include <configs/ecovec.h>
  14
  15         .global lowlevel_init
  16
  17         .text
  18         .align  2
  19
  20 lowlevel_init:
  21
  22         /* jump to CONFIG_ECOVEC_ROMIMAGE_ADDR if bit 1 of PVDR_A */
  23         mov.l   PVDR_A, r1
  24         mov.l   PVDR_D, r2
  25         mov.b   @r1, r0
  26         tst     r0, r2
  27         bt      1f
  28         mov.l   JUMP_A, r1
  29         jmp     @r1
  30         nop
  31
  32 1:
  33         /* Disable watchdog */
  34         write16 RWTCSR_A, RWTCSR_D
  35
  36         /* MMU Disable */
  37         write32 MMUCR_A, MMUCR_D
  38
  39         /* Setup clocks */
  40         write32 PLLCR_A, PLLCR_D
  41         write32 FRQCRA_A, FRQCRA_D
  42         write32 FRQCRB_A, FRQCRB_D
  43
  44         wait_timer TIMER_D
  45
  46         write32 MMSELR_A, MMSELR_D
  47
  48         /* Srtup BSC */
  49         write32 CMNCR_A, CMNCR_D
  50         write32 CS0BCR_A, CS0BCR_D
  51         write32 CS0WCR_A, CS0WCR_D
  52
  53         wait_timer TIMER_D
  54
  55         /* Setup SDRAM */
  56         write32 DBPDCNT0_A,     DBPDCNT0_D0
  57         write32 DBCONF_A,       DBCONF_D
  58         write32 DBTR0_A,        DBTR0_D
  59         write32 DBTR1_A,        DBTR1_D
  60         write32 DBTR2_A,        DBTR2_D
  61         write32 DBTR3_A,        DBTR3_D
  62         write32 DBKIND_A,       DBKIND_D
  63         write32 DBCKECNT_A,     DBCKECNT_D
  64
  65         wait_timer TIMER_D
  66
  67         write32 DBCMDCNT_A,     DBCMDCNT_D0
  68         write32 DBMRCNT_A, DBMRCNT_D0
  69         write32 DBMRCNT_A, DBMRCNT_D1
  70         write32 DBMRCNT_A, DBMRCNT_D2
  71         write32 DBMRCNT_A, DBMRCNT_D3
  72         write32 DBCMDCNT_A, DBCMDCNT_D0
  73         write32 DBCMDCNT_A, DBCMDCNT_D1
  74         write32 DBCMDCNT_A, DBCMDCNT_D1
  75         write32 DBMRCNT_A, DBMRCNT_D4
  76         write32 DBMRCNT_A, DBMRCNT_D5
  77         write32 DBMRCNT_A, DBMRCNT_D6
  78
  79         wait_timer TIMER_D
  80
  81         write32 DBEN_A, DBEN_D
  82         write32 DBRFPDN1_A, DBRFPDN1_D
  83         write32 DBRFPDN2_A, DBRFPDN2_D
  84         write32 DBCMDCNT_A, DBCMDCNT_D0
  85
  86
  87         /* Dummy read */
  88         mov.l DUMMY_A ,r1
  89         synco
  90         mov.l @r1, r0
  91         synco
  92
  93         mov.l SDRAM_A ,r1
  94         synco
  95         mov.l @r1, r0
  96         synco
  97         wait_timer TIMER_D
  98
  99         add #4, r1
 100         synco
 101         mov.l @r1, r0
 102         synco
 103         wait_timer TIMER_D
 104
 105         add #4, r1
 106         synco
 107         mov.l @r1, r0
 108         synco
 109         wait_timer TIMER_D
 110
 111         add #4, r1
 112         synco
 113         mov.l @r1, r0
 114         synco
 115         wait_timer TIMER_D
 116
 117         write32 DBCMDCNT_A, DBCMDCNT_D0
 118         write32 DBCMDCNT_A, DBCMDCNT_D1
 119         write32 DBPDCNT0_A, DBPDCNT0_D1
 120         write32 DBRFPDN0_A, DBRFPDN0_D
 121
 122         wait_timer TIMER_D
 123
 124         write32 CCR_A, CCR_D
 125
 126         stc     sr, r0
 127         mov.l   SR_MASK_D, r1
 128         and     r1, r0
 129         ldc     r0, sr
 130
 131         rts
 132
 133         .align  2
 134
 135 PVDR_A:         .long   PVDR
 136 PVDR_D:         .long   0x00000001
 137 JUMP_A:         .long   CONFIG_ECOVEC_ROMIMAGE_ADDR
 138 TIMER_D:        .long   64
 139 RWTCSR_A:       .long   RWTCSR
 140 RWTCSR_D:       .long   0x0000A507
 141 MMUCR_A:        .long   MMUCR
 142 MMUCR_D:        .long   0x00000004
 143 PLLCR_A:        .long   PLLCR
 144 PLLCR_D:        .long   0x00004000
 145 FRQCRA_A:       .long   FRQCRA
 146 FRQCRA_D:       .long   0x8E003508
 147 FRQCRB_A:       .long   FRQCRB
 148 FRQCRB_D:       .long   0x0
 149 MMSELR_A:       .long   MMSELR
 150 MMSELR_D:       .long   0xA5A50000
 151 CMNCR_A:        .long   CMNCR
 152 CMNCR_D:        .long   0x00000013
 153 CS0BCR_A:       .long   CS0BCR
 154 CS0BCR_D:       .long   0x11110400
 155 CS0WCR_A:       .long   CS0WCR
 156 CS0WCR_D:       .long   0x00000440
 157 DBPDCNT0_A:     .long   DBPDCNT0
 158 DBPDCNT0_D0: .long      0x00000181
 159 DBPDCNT0_D1: .long      0x00000080
 160 DBCONF_A:       .long   DBCONF
 161 DBCONF_D:       .long   0x015B0002
 162 DBTR0_A:        .long   DBTR0
 163 DBTR0_D:        .long   0x03061502
 164 DBTR1_A:        .long   DBTR1
 165 DBTR1_D:        .long   0x02020102
 166 DBTR2_A:        .long   DBTR2
 167 DBTR2_D:        .long   0x01090305
 168 DBTR3_A:        .long   DBTR3
 169 DBTR3_D:        .long   0x00000002
 170 DBKIND_A:       .long   DBKIND
 171 DBKIND_D:       .long   0x00000005
 172 DBCKECNT_A:     .long   DBCKECNT
 173 DBCKECNT_D:     .long   0x00000001
 174 DBCMDCNT_A:     .long   DBCMDCNT
 175 DBCMDCNT_D0:.long       0x2
 176 DBCMDCNT_D1:.long       0x4
 177 DBMRCNT_A:      .long   DBMRCNT
 178 DBMRCNT_D0:     .long   0x00020000
 179 DBMRCNT_D1:     .long   0x00030000
 180 DBMRCNT_D2:     .long   0x00010040
 181 DBMRCNT_D3:     .long   0x00000532
 182 DBMRCNT_D4:     .long   0x00000432
 183 DBMRCNT_D5:     .long   0x000103C0
 184 DBMRCNT_D6:     .long   0x00010040
 185 DBEN_A:         .long   DBEN
 186 DBEN_D:         .long   0x01
 187 DBRFPDN0_A:     .long   DBRFPDN0
 188 DBRFPDN1_A:     .long   DBRFPDN1
 189 DBRFPDN2_A:     .long   DBRFPDN2
 190 DBRFPDN0_D:     .long   0x00010000
 191 DBRFPDN1_D:     .long   0x00000613
 192 DBRFPDN2_D:     .long   0x238C003A
 193 SDRAM_A:        .long   0xa8000000
 194 DUMMY_A:        .long   0x0c400000
 195 CCR_A:          .long   CCR
 196 CCR_D:          .long   0x0000090B
 197 SR_MASK_D:      .long   0xEFFFFF0F