2 * board/renesas/koelsch/koelsch.c
4 * Copyright (C) 2013 Renesas Electronics Corporation
6 * SPDX-License-Identifier: GPL-2.0
12 #include <asm/processor.h>
13 #include <asm/mach-types.h>
15 #include <asm/errno.h>
16 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/rmobile.h>
24 DECLARE_GLOBAL_DATA_PTR;
28 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
29 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
32 writel(0xA5A5A500, &rwdt->rwtcsra);
33 writel(0xA5A5A500, &swdt->swtcsra);
39 #define MSTPSR1 0xE6150038
40 #define SMSTPCR1 0xE6150134
41 #define TMU0_MSTP125 (1 << 25)
43 #define MSTPSR7 0xE61501C4
44 #define SMSTPCR7 0xE615014C
45 #define SCIF0_MSTP721 (1 << 21)
47 #define MSTPSR8 0xE61509A0
48 #define SMSTPCR8 0xE6150990
49 #define ETHER_MSTP813 (1 << 13)
51 #define mstp_setbits(type, addr, saddr, set) \
52 out_##type((saddr), in_##type(addr) | (set))
53 #define mstp_clrbits(type, addr, saddr, clear) \
54 out_##type((saddr), in_##type(addr) & ~(clear))
55 #define mstp_setbits_le32(addr, saddr, set) \
56 mstp_setbits(le32, addr, saddr, set)
57 #define mstp_clrbits_le32(addr, saddr, clear) \
58 mstp_clrbits(le32, addr, saddr, clear)
60 int board_early_init_f(void)
62 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
65 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
68 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
73 void arch_preboot_os(void)
76 mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
79 /* LSI pin pull-up control */
80 #define PUPR5 0xe6060114
81 #define PUPR5_ETH 0x3FFC0000
82 #define PUPR5_ETH_MAGIC (1 << 27)
85 /* adress of boot parameters */
86 gd->bd->bi_boot_params = KOELSCH_SDRAM_BASE + 0x100;
88 /* Init PFC controller */
89 r8a7791_pinmux_init();
92 gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
93 gpio_request(GPIO_FN_ETH_RX_ER, NULL);
94 gpio_request(GPIO_FN_ETH_RXD0, NULL);
95 gpio_request(GPIO_FN_ETH_RXD1, NULL);
96 gpio_request(GPIO_FN_ETH_LINK, NULL);
97 gpio_request(GPIO_FN_ETH_REFCLK, NULL);
98 gpio_request(GPIO_FN_ETH_MDIO, NULL);
99 gpio_request(GPIO_FN_ETH_TXD1, NULL);
100 gpio_request(GPIO_FN_ETH_TX_EN, NULL);
101 gpio_request(GPIO_FN_ETH_TXD0, NULL);
102 gpio_request(GPIO_FN_ETH_MDC, NULL);
103 gpio_request(GPIO_FN_IRQ0, NULL);
105 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
106 gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
107 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
109 gpio_direction_output(GPIO_GP_5_22, 0);
111 gpio_set_value(GPIO_GP_5_22, 1);
117 #define CXR24 0xEE7003C0 /* MAC address high register */
118 #define CXR25 0xEE7003C8 /* MAC address low register */
119 int board_eth_init(bd_t *bis)
121 #ifdef CONFIG_SH_ETHER
124 unsigned char enetaddr[6];
126 ret = sh_eth_initialize(bis);
127 if (!eth_getenv_enetaddr("ethaddr", enetaddr))
130 /* Set Mac address */
131 val = enetaddr[0] << 24 | enetaddr[1] << 16 |
132 enetaddr[2] << 8 | enetaddr[3];
135 val = enetaddr[4] << 8 | enetaddr[5];
146 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
147 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
152 /* koelsch has KSZ8041NL/RNL */
153 #define PHY_CONTROL1 0x1E
154 #define PHY_LED_MODE 0xC0000
155 #define PHY_LED_MODE_ACK 0x4000
156 int board_phy_config(struct phy_device *phydev)
158 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
159 ret &= ~PHY_LED_MODE;
160 ret |= PHY_LED_MODE_ACK;
161 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
166 const struct rmobile_sysinfo sysinfo = {
167 CONFIG_RMOBILE_BOARD_STRING
170 void dram_init_banksize(void)
172 gd->bd->bi_dram[0].start = KOELSCH_SDRAM_BASE;
173 gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE;
176 int board_late_init(void)
181 void reset_cpu(ulong addr)
185 i2c_set_bus_num(2); /* PowerIC connected to ch2 */
186 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
188 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);