2 * Copyright (C) 2012 Renesas Electronics Europe Ltd.
3 * Copyright (C) 2012 Phil Edworthy
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu
7 * Based on board/renesas/rsk7264/lowlevel_init.S
9 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/processor.h>
14 #include <asm/macro.h>
22 /* Flush and enable caches (data cache in write-through mode) */
23 write32 CCR1_A ,CCR1_D
26 write16 WTCSR_A, WTCSR_D
27 write16 WTCNT_A, WTCNT_D
29 /* Disable Register Bank interrupts */
30 write16 IBNR_A, IBNR_D
32 /* Set clocks based on 13.225MHz xtal */
33 write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */
35 /* Enable all peripherals */
36 write8 STBCR3_A, STBCR3_D
37 write8 STBCR4_A, STBCR4_D
38 write8 STBCR5_A, STBCR5_D
39 write8 STBCR6_A, STBCR6_D
40 write8 STBCR7_A, STBCR7_D
41 write8 STBCR8_A, STBCR8_D
42 write8 STBCR9_A, STBCR9_D
43 write8 STBCR10_A, STBCR10_D
46 write16 PJCR3_A, PJCR3_D /* TXD7 */
47 write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */
49 /* Configure bus (CS0) */
50 write16 PFCR3_A, PFCR3_D /* A24 */
51 write16 PFCR2_A, PFCR2_D /* A23 and CS1# */
52 write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */
53 write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
54 write32 CS0WCR_A, CS0WCR_D
55 write32 CS0BCR_A, CS0BCR_D
57 /* Configure SDRAM (CS3) */
58 write16 PCCR2_A, PCCR2_D /* CS3# */
59 write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */
60 write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
61 write32 CS3BCR_A, CS3BCR_D
62 write32 CS3WCR_A, CS3WCR_D
63 write32 SDCR_A, SDCR_D
64 write32 RTCOR_A, RTCOR_D
65 write32 RTCSR_A, RTCSR_D
67 /* Configure ethernet (CS1) */
68 write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */
69 write16 PHCR0_A, PHCR0_D
70 write16 PFCR2_A, PFCR2_D /* CS1# */
71 write32 CS1BCR_A, CS1BCR_D /* Big endian */
72 write32 CS1WCR_A, CS1WCR_D /* 1 cycle */
73 write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */
74 write16 PJIOR1_A, PJIOR1_D
95 CCR1_D: .long 0x0000090B
97 STBCR3_A: .long 0xFFFE0408
98 STBCR4_A: .long 0xFFFE040C
99 STBCR5_A: .long 0xFFFE0410
100 STBCR6_A: .long 0xFFFE0414
101 STBCR7_A: .long 0xFFFE0418
102 STBCR8_A: .long 0xFFFE041C
103 STBCR9_A: .long 0xFFFE0440
104 STBCR10_A: .long 0xFFFE0444
105 STBCR3_D: .long 0x0000001A
106 STBCR4_D: .long 0x00000000
107 STBCR5_D: .long 0x00000000
108 STBCR6_D: .long 0x00000000
109 STBCR7_D: .long 0x00000012
110 STBCR8_D: .long 0x00000009
111 STBCR9_D: .long 0x00000000
112 STBCR10_D: .long 0x00000010
114 WTCSR_A: .long 0xFFFE0000
115 WTCNT_A: .long 0xFFFE0002
116 WTCSR_D: .word 0xA518
117 WTCNT_D: .word 0x5A00
119 IBNR_A: .long 0xFFFE080E
122 FRQCR_A: .long 0xFFFE0010
123 FRQCR_D: .word 0x0015
126 PJCR3_A: .long 0xFFFE3908
127 PJCR3_D: .word 0x5000
129 PECR1_A: .long 0xFFFE388C
130 PECR1_D: .word 0x2011
133 PFCR3_A: .long 0xFFFE38A8
134 PFCR2_A: .long 0xFFFE38AA
135 PBCR5_A: .long 0xFFFE3824
136 PFCR3_D: .word 0x0010
137 PFCR2_D: .word 0x0101
138 PBCR5_D: .word 0x0111
140 CS0WCR_A: .long 0xFFFC0028
141 CS0WCR_D: .long 0x00000341
142 CS0BCR_A: .long 0xFFFC0004
143 CS0BCR_D: .long 0x00000400
145 PCCR2_A: .long 0xFFFE384A
146 PCCR1_A: .long 0xFFFE384C
147 PCCR0_A: .long 0xFFFE384E
148 PCCR2_D: .word 0x0001
149 PCCR1_D: .word 0x1111
150 PCCR0_D: .word 0x1111
152 CS3BCR_A: .long 0xFFFC0010
153 CS3BCR_D: .long 0x00004400
154 CS3WCR_A: .long 0xFFFC0034
155 CS3WCR_D: .long 0x00004912
156 SDCR_A: .long 0xFFFC004C
157 SDCR_D: .long 0x00000811
158 RTCOR_A: .long 0xFFFC0058
159 RTCOR_D: .long 0xA55A0035
160 RTCSR_A: .long 0xFFFC0050
161 RTCSR_D: .long 0xA55A0010
163 SDRAM_MODE: .long 0xFFFC5460
164 REPEAT_D: .long 0x000033F1
166 PHCR1_A: .long 0xFFFE38EC
167 PHCR0_A: .long 0xFFFE38EE
168 PHCR1_D: .word 0x2222
169 PHCR0_D: .word 0x2222
171 CS1BCR_A: .long 0xFFFC0008
172 CS1BCR_D: .long 0x00000400
173 CS1WCR_A: .long 0xFFFC002C
174 CS1WCR_D: .long 0x00000080
175 PJDR1_A: .long 0xFFFE3914
176 PJDR1_D: .word 0x0000
178 PJIOR1_A: .long 0xFFFE3910
179 PJIOR1_D: .word 0x8000