2 * board/renesas/ulcb/ulcb.c
3 * This file is ULCB board support.
5 * Copyright (C) 2017 Renesas Electronics Corporation
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/platform_data/serial_sh.h>
15 #include <asm/processor.h>
16 #include <asm/mach-types.h>
18 #include <linux/errno.h>
19 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/rmobile.h>
23 #include <asm/arch/rcar-mstp.h>
24 #include <asm/arch/sh_sdhi.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 #define CPGWPCR 0xE6150904
31 #define CPGWPR 0xE615090C
33 #define CLK2MHZ(clk) (clk / 1000 / 1000)
36 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
37 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
40 writel(0xA5A5A500, &rwdt->rwtcsra);
41 writel(0xA5A5A500, &swdt->swtcsra);
43 writel(0xA5A50000, CPGWPCR);
44 writel(0xFFFFFFFF, CPGWPR);
47 #define GSX_MSTP112 BIT(12) /* 3DG */
48 #define TMU0_MSTP125 BIT(25) /* secure */
49 #define TMU1_MSTP124 BIT(24) /* non-secure */
50 #define SCIF2_MSTP310 BIT(10) /* SCIF2 */
51 #define ETHERAVB_MSTP812 BIT(12)
52 #define DVFS_MSTP926 BIT(26)
53 #define HSUSB_MSTP704 BIT(4) /* HSUSB */
55 int board_early_init_f(void)
57 /* TMU0,1 */ /* which use ? */
58 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
60 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
62 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
64 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
66 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
72 /* R/- 32 Power status register 2(3DG) */
73 #define SYSC_PWRSR2 0xE6180100
74 /* -/W 32 Power resume control register 2 (3DG) */
75 #define SYSC_PWRONCR2 0xE618010C
77 /* HSUSB block registers */
78 #define HSUSB_REG_LPSTS 0xE6590102
79 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
80 #define HSUSB_REG_UGCTRL2 0xE6590184
81 #define HSUSB_REG_UGCTRL2_USB0SEL 0x30
82 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
86 /* adress of boot parameters */
87 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
89 /* Init PFC controller */
90 #if defined(CONFIG_R8A7795)
91 r8a7795_pinmux_init();
92 #elif defined(CONFIG_R8A7796)
93 r8a7796_pinmux_init();
97 setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
99 /* Configure the HSUSB block */
100 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
102 clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
103 HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
104 /* low power status */
105 setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
107 #ifdef CONFIG_RENESAS_RAVB
108 /* EtherAVB Enable */
110 gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
111 gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
112 gpio_request(GPIO_GFN_AVB_LINK, NULL);
113 gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
114 gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
115 gpio_request(GPIO_GFN_AVB_MDC, NULL);
118 gpio_request(GPIO_IFN_AVB_MDC, NULL);
119 gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
120 gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
121 gpio_request(GPIO_IFN_AVB_LINK, NULL);
122 gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
123 gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
125 gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
127 gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
129 gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
132 gpio_request(GPIO_GP_2_10, NULL);
133 gpio_direction_output(GPIO_GP_2_10, 0);
135 gpio_set_value(GPIO_GP_2_10, 1);
141 gpio_request(GPIO_GFN_SD0_DAT0, NULL);
142 gpio_request(GPIO_GFN_SD0_DAT1, NULL);
143 gpio_request(GPIO_GFN_SD0_DAT2, NULL);
144 gpio_request(GPIO_GFN_SD0_DAT3, NULL);
145 gpio_request(GPIO_GFN_SD0_CLK, NULL);
146 gpio_request(GPIO_GFN_SD0_CMD, NULL);
147 gpio_request(GPIO_GFN_SD0_CD, NULL);
148 gpio_request(GPIO_GFN_SD0_WP, NULL);
150 gpio_request(GPIO_GP_5_2, NULL);
151 gpio_request(GPIO_GP_5_1, NULL);
152 gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
153 gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
155 /* SDHI1/SDHI2 eMMC */
156 gpio_request(GPIO_GFN_SD1_DAT0, NULL);
157 gpio_request(GPIO_GFN_SD1_DAT1, NULL);
158 gpio_request(GPIO_GFN_SD1_DAT2, NULL);
159 gpio_request(GPIO_GFN_SD1_DAT3, NULL);
160 gpio_request(GPIO_GFN_SD2_DAT0, NULL);
161 gpio_request(GPIO_GFN_SD2_DAT1, NULL);
162 gpio_request(GPIO_GFN_SD2_DAT2, NULL);
163 gpio_request(GPIO_GFN_SD2_DAT3, NULL);
164 gpio_request(GPIO_GFN_SD2_CLK, NULL);
165 #if defined(CONFIG_R8A7795)
166 gpio_request(GPIO_GFN_SD2_CMD, NULL);
167 #elif defined(CONFIG_R8A7796)
168 gpio_request(GPIO_FN_SD2_CMD, NULL);
170 #error Only R8A7795 and R87796 is supported
172 gpio_request(GPIO_GP_5_3, NULL);
173 gpio_request(GPIO_GP_5_9, NULL);
174 gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
175 gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
183 gd->ram_size = PHYS_SDRAM_1_SIZE;
184 #if (CONFIG_NR_DRAM_BANKS >= 2)
185 gd->ram_size += PHYS_SDRAM_2_SIZE;
187 #if (CONFIG_NR_DRAM_BANKS >= 3)
188 gd->ram_size += PHYS_SDRAM_3_SIZE;
190 #if (CONFIG_NR_DRAM_BANKS >= 4)
191 gd->ram_size += PHYS_SDRAM_4_SIZE;
197 int dram_init_banksize(void)
199 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
200 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
201 #if (CONFIG_NR_DRAM_BANKS >= 2)
202 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
203 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
205 #if (CONFIG_NR_DRAM_BANKS >= 3)
206 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
207 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
209 #if (CONFIG_NR_DRAM_BANKS >= 4)
210 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
211 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
216 const struct rmobile_sysinfo sysinfo = {
217 CONFIG_RCAR_BOARD_STRING